[[File:AxelLite-reset-scheme.png | 800px]]
The available === PMIC_VSNVS ===Some signals that are related to reset signals circuitry are described pulled-up to PMIC_VSNVS. This voltage is generated by PMIC PF0100's VSNVS LDO/Switch and its actual value depends on:* voltage applied to PMICS's VIN pin** in detail case of AxelLite this pin is connected to 3.3VIN power rail* voltage applied to PMICS's LICELL pin** in the following sectionscase of AxelLite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL)* PMIC's VSNVSCTL register configuration.Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level'''. For more details please refer to section ''VSNVS LDO/Switch'' of ''MMPF0100 Advance Information'' document.
=== CPU_PORn ===
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.
=== Handling CPU initiated reset ===
'''By default, MX6 processor does not assert any external signal when it initiates a reset sequence'''. This behaviour can be changed by acting on WDOG_RESET_B_DEB signal configuration. This signal is driven by MX6's watchdog timer (WDT).
The two typical scenarios are:
# WDOG_RESET_B_DEB is not used (default): in this case a CPU initiated reset sequence does not reset external devices such as SPI NOR flash memory. '''This may be critical'''. For example if boot memory is not reset properly, processor might be unable to boot correctly.
# WDOG_RESET_B_DEB is used: in this case a CPU initiated reset asserts WDOG_RESET_B_DEB signal that, in turn, can be used to reset external devices. To implement this solution:
#* software reset routines must configure WDT in order to assert WDOG_RESET_B_DEB signal
#* WDOG_RESET_B_DEB must be configured properly at IOMUX controller level
#* when asserted, WDOG_RESET_B_DEB must assert in turn either AxelLite's PMIC_PWRON or AxelLite's CPU_PORn signal at carrier board level (see [[AxelEVB-Lite]] schematics as an example). In case PMIC_PWRON is asserted, a complete power on cycle is perfomed and PMIC is reset too. In case CPU_PORn is asserted instead, PMIC is not reset because its RESETBMCU pad is output only.
WDOG_RESET_B_DEB can be routed to SD1_DATA2 or SD1_DATA3 pads=== Handling CPU-initiated software reset ==='''By default, MX6 processor does not assert any external signal when it initiates a software reset sequence. For more details please see descriptions ofIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 and IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 Also default software reset implementation does not guarantee that all processor registers in chapter are reset properly''IOMUX controller'. For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor' s watchdog timer (WDT), provides a full hardware reset in case a software reset is issued. This technique is implemented in [[Axel_Embedded_Linux_Kit_(XELK)|XELK]]. At software level, U-Boot and Linux kernel software reset routines make use of processor Reference Manual's WDT #2 to assert the WDOG2_B reset signal. This signal in turn is routed to GPIO_1 pad (MUX mode = 1). About WDTAt hardware level, this signal is AC-coupled to a 3-state output buffer (please refer to ''Watchdog Timer'' chapter insteadU22 chip of [[AxelEVB-Lite]] carrier board), driving PMIC_PWRON.
