Reset scheme (AxelLite)

Info Box Applies to Axel Lite

Reset scheme and control signals

The following picture shows the simplified block diagram of reset scheme and voltage monitoring.

PMIC_VSNVS

Some signals that are related to reset circuitry are pulled-up to PMIC_VSNVS. This voltage is generated by PMIC PF0100's VSNVS LDO/Switch and its actual value depends on:

• voltage applied to PMICS's VIN pin
  • in case of AxelLite this pin is connected to 3.3VIN power rail
• voltage applied to PMICS's LICELL pin
  • in case of AxelLite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL)
• PMIC's VSNVSCTL register configuration.

Hence it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level.

For more details please refer to section VSNVS LDO/Switch of MMPF0100 Advance Information document.

CPU_PORn

The following devices can assert this active-low signal:

• PMIC
• multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition

Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.

Handling CPU initiated reset

By default, MX6 processor does not assert any external signal when it initiates a reset sequence. This behaviour can be changed by acting on WDOG_RESET_B_DEB signal configuration. This signal is driven by MX6's watchdog timer (WDT).

The two typical scenarios are:

1. WDOG_RESET_B_DEB is not used (default): in this case a CPU initiated reset sequence does not reset external devices such as SPI NOR flash memory. This may be critical. For example if boot memory is not reset properly, processor might be unable to boot correctly.
2. WDOG_RESET_B_DEB is used: in this case a CPU initiated reset asserts WDOG_RESET_B_DEB signal that, in turn, can be used to reset external devices. To implement this solution:
   • software reset routines must configure WDT in order to assert WDOG_RESET_B_DEB signal
   • WDOG_RESET_B_DEB must be configured properly at IOMUX controller level
   • when asserted, WDOG_RESET_B_DEB must assert in turn either AxelLite's PMIC_PWRON or AxelLite's CPU_PORn signal at carrier board level (see AxelEVB-Lite schematics as an example). In case PMIC_PWRON is asserted, a complete power on cycle is perfomed and PMIC is reset too. In case CPU_PORn is asserted instead, PMIC is not reset because its RESETBMCU pad is output only.

WDOG_RESET_B_DEB can be routed to SD1_DATA2 or SD1_DATA3 pads. For more details please see descriptions of IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 and IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 registers in chapter IOMUX controller of processor Reference Manual. About WDT, please refer to Watchdog Timer chapter instead.