Programmable logic (BoraLite)

Info Box Applies to BORA Lite

Introduction

The following paragraphs describe in detail the available PL I/O pins and how they are routed to the BORA Lite connector. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, Bora Lite design allows carrier board to power two PL banks in order to achieve complete flexibility in terms of I/O voltage levels too. For more details about PCB design considerations, please refer to the Advanced routing and carrier board design guidelines article.

The following table reports the I/O banks characteristics:

FPGA Bank	Type	I/O Voltage	Voltage Pins	Notes
Bank 35	High range (HR)	User defined VIO=FPGA_VDDIO_BANK35 1.8 to 3.3V	J1.186 J1.188 J1.192 J1.201
Bank 34	High range (HR)	User defined VIO=FPGA_VDDIO_BANK34 1.8 to 3.3V	J1.77 J1.124 J1.127 J1.129
Bank 13	High range (HR)	User defined VIO=FPGA_VDDIO_BANK13 1.8 to 3.3V	J1.41 J1.67 J3.97 J3.98 J3.99	Bank 13 is available only with Zynq XC7Z020 part number. Although this bank is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pins must not be left open and must be connected anyway, either to ground or to an external I/O voltage.

Each user I/O is labeled IO_LXXY_Tn_ZZZ_ADi_#, where:

• IO indicates a user I/O pin.
• L indicates a differential pair, with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair.
• Tn indicates the memory byte group [0-3]
• ZZZ indicates a MRCC, SRCC or DQS pin
• ADi indicates a XADC (analog-to-digital converter) differential auxiliary analog input [0–15].
• # indicates the bank number.

Highlighted rows are related to signals that are used for particular functions into the SOM.

FPGA Bank 34

The following table reports the available pins connected to bank 34:

Pin Name	Conn. Pin	Notes
IO_0_34	J1.79
IO_25_34	J1.81
IO_L1P_T0_34	J1.84
IO_L1N_T0_34	J1.86
IO_L2P_T0_34	J1.93
IO_L2N_T0_34	J1.95
IO_L3N_T0_DQS_34	J1.88
IO_L3P_T0_DQS_PUDC_B_34	J1.90	Internally connected to a 10K pull-up to VDDIO_BANK34
IO_L4P_T0_34	J1.97
IO_L4N_T0_34	J1.99
IO_L5N_T0_34	J1.92
IO_L5P_T0_34	J1.94
IO_L6P_T0_34	J1.110
IO_L6N_T0_VREF_34	J1.112
IO_L7P_T1_34	J1.89
IO_L7N_T1_34	J1.91
IO_L8N_T1_34	J1.83
IO_L8P_T1_34	J1.85
IO_L9P_T1_DQS_34	J1.106
IO_L9N_T1_DQS_34	J1.108
IO_L10P_T1_34	J1.96
IO_L10N_T1_34	J1.98
IO_L11P_T1_SRCC_34	J1.105
IO_L11N_T1_SRCC_34	J1.107
IO_L12P_T1_MRCC_34	J1.130	Optionally internally connected to RTC/INT_SQW
IO_L12N_T1_MRCC_34	J1.132
IO_L13N_T2_MRCC_34	J1.138
IO_L13P_T2_MRCC_34	J1.140	Optionally internally connected to RTC_32KHZ
IO_L14P_T2_SRCC_34	J1.142
IO_L14N_T2_SRCC_34	J1.144
IO_L15P_T2_DQS_34	J1.118
IO_L15N_T2_DQS_34	J1.120
IO_L16N_T2_34	J1.115
IO_L16P_T2_34	J1.117
IO_L17P_T2_34	J1.111
IO_L17N_T2_34	J1.113
IO_L18P_T2_34	J1.101
IO_L18N_T2_34	J1.103
IO_L19N_T3_VREF_34	J1.116
IO_L19P_T3_34	J1.114
IO_L20P_T3_34	J1.134
IO_L20N_T3_34	J1.136
IO_L21P_T3_DQS_34	J1.102
IO_L21N_T3_DQS_34	J1.104
IO_L22P_T3_34	J1.126
IO_L22N_T3_34	J1.128
IO_L23N_T3_34	J1.123
IO_L23P_T3_34	J1.125
IO_L24P_T3_34	J1.119
IO_L24N_T3_34	J1.121