The following paragraphs describe in detail the available PL I/O pins and how they are routed to the BORA Lite connector. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, Bora Lite design allows carrier board to power two PL banks in order to achieve complete flexibility in terms of I/O voltage levels too.
For more details about PCB design considerations, please refer to the [[Integration_guide_(BoraLite)BORA_Lite_SOM/BORA_Lite_Evaluation_Kit/Carrier_board_design/Integration_Guide#Advanced_routing_and_carrier_board_design_guidelines | Advanced routing and carrier board design guidelines]] article.
The following table reports the I/O banks characteristics:
!Notes
|-
|Bank 3513
|High range (HR)
|User defined<br>VIO=FPGA_VDDIO_BANK35FPGA_VDDIO_BANK13<br>'''1.8 to 3.3V'''|J1.18641<br>J1.18867<br>J1J3.97<br>J3.19298<br>J1J3.20199|Bank 13 is available only with Zynq XC7Z020 part number. Although this bank is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pins must not be left open and must be connected anyway, either to ground or to an external I/O voltage.
|-
|Bank 34
|
|-
|Bank 1335
|High range (HR)
|User defined<br>VIO=FPGA_VDDIO_BANK13FPGA_VDDIO_BANK35<br>'''1.8 to 3.3V'''|J1.41186<br>J1.67188<br>J3J1.97192<br>J3.98<br>J3J1.99201|Bank 13 is available only with Zynq XC7Z020 part number. Although this bank is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pins must not be left open and must be connected anyway, either to ground or to an external I/O voltage.
|-
|}
Highlighted rows are related to signals that are used for particular functions into the SOM.
=== FPGA Bank 13 (Zynq 7020 only) === N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, '''VDDIO_BANK13 pins must not be left open and must be connected anyway''', either to ground or to an external I/O voltage as described in [[Programmable_logic_(BoraLite)#Introduction | I/O banks table]]. The following table reports the available pins connected to bank 13: {| class="wikitable" border="1"| align="left" style="background:#f0f0f0;"|'''Pin Name'''| align="left" style="background:#f0f0f0;"|'''Conn. Pin'''| align="left" style="background:#f0f0f0;"|'''Notes'''|-| IO_L11P_T1_SRCC_13 || J1.49 || |-| IO_L11N_T1_SRCC_13 || J1.51 || |-| IO_L12P_T1_MRCC_13 || J1.62 || |-| IO_L12N_T1_MRCC_13 || J1.64 || |-| IO_L13N_T2_MRCC_13 || J1.53 || |-| IO_L13P_T2_MRCC_13 || J1.55 || |-| IO_L14N_T2_SRCC_13 || J1.69 || |-| IO_L14P_T2_SRCC_13 || J1.71 || |-| IO_L15N_T2_DQS_13 || J1.59 || |-| IO_L15P_T2_DQS_13 || J1.61 || |-| IO_L16P_T2_13 || J1.63 || |-| IO_L16N_T2_13 || J1.65 || |-| IO_L17N_T2_13 || J1.58 || |-| IO_L17P_T2_13 || J1.60 || |-| IO_L18P_T2_13 || J1.70 || |-| IO_L18N_T2_13 || J1.72 || |-| IO_L19P_T3_13 || J1.66 || |-| IO_L19N_T3_VREF_13 || J1.68 || |-| IO_L20P_T3_13 || J1.78 || |-| IO_L20N_T3_13 || J1.80 || |-| IO_L21N_T3_DQS_13 || J1.74 || |-| IO_L21P_T3_DQS_13 || J1.76 || |-| IO_L22P_T3_13 || J1.45 || |-| IO_L22N_T3_13 ||J1.47 || |-| IO_L6N_T0_VREF_13 || J1.43 || |-|} ====Routing information====Routing implemented on Bora SoM allows the use of bank 13's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent. Pairs are highlighted with different colors. When used as differential pairs, differential impedence is 100 Ohm. When used as single-ended signals, impedence is 50 Ohm. {| class="wikitable" border="1"| align="center" style="background:#f0f0f0;"|'''Bora pin name'''| align="center" style="background:#f0f0f0;"|'''Individual net length<br>[mils]'''| align="center" style="background:#f0f0f0;"|'''Intra-pair match<br>[mils]'''| align="center" style="background:#f0f0f0;"|'''Inter-pair match<br>[mils]'''| align="center" style="background:#f0f0f0;"|'''Group Name'''|-| IO_L11N_T1_SRCC_13||align="center"|963.29||align="center"|5||align="center"|360||BANK13 Diff group 1|-| IO_L11P_T1_SRCC_13||align="center"|965.44||align="center"|5||align="center"|360||BANK13 Diff group 1|- style="background: gray"| IO_L12N_T1_MRCC_13||align="center"|1002.27||align="center"|5||align="center"|360||BANK13 Diff group 1|- style="background: gray"| IO_L12P_T1_MRCC_13||align="center"|998.73||align="center"|5||align="center"|360||BANK13 Diff group 1|-| IO_L13N_T2_MRCC_13||align="center"|819.57||align="center"|5||align="center"|360||BANK13 Diff group 1|-| IO_L13P_T2_MRCC_13||align="center"|819.57||align="center"|5||align="center"|360||BANK13 Diff group 1|- style="background: gray"| IO_L14N_T2_SRCC_13||align="center"|820.26||align="center"|5||align="center"|360||BANK13 Diff group 1|- style="background: gray"| IO_L14P_T2_SRCC_13||align="center"|821.43||align="center"|5||align="center"|360||BANK13 Diff group 1|-| IO_L15N_T2_DQS_13||align="center"|885.06||align="center"|5||align="center"|360||BANK13 Diff group 1|-| IO_L15P_T2_DQS_13||align="center"|885.06||align="center"|5||align="center"|360||BANK13 Diff group 1|- style="background: gray"| IO_L16N_T2_13||align="center"|922.83||align="center"|5||align="center"|360||BANK13 Diff group 1|- style="background: gray"| IO_L16P_T2_13||align="center"|922.83||align="center"|5||align="center"|360||BANK13 Diff group 1|-| IO_L17N_T2_13||align="center"|1007.3||align="center"|5||align="center"|360||BANK13 Diff group 1|-| IO_L17P_T2_13||align="center"|1008.75||align="center"|5||align="center"|360||BANK13 Diff group 1|- style="background: gray"| IO_L18N_T2_13||align="center"|827.46||align="center"|5||align="center"|360||BANK13 Diff group 1|- style="background: gray"| IO_L18P_T2_13||align="center"|829.35||align="center"|5||align="center"|360||BANK13 Diff group 1|-| IO_L19N_T3_VREF_13||align="center"|802.16||align="center"|5||align="center"|360||BANK13 Diff group 1|-| IO_L19P_T3_13||align="center"|802.16||align="center"|5||align="center"|360||BANK13 Diff group 1|- style="background: gray"| IO_L20N_T3_13||align="center"|653.65||align="center"|5||align="center"|360||BANK13 Diff group 1|- style="background: gray"| IO_L20P_T3_13||align="center"|655.59||align="center"|5||align="center"|360||BANK13 Diff group 1|-| IO_L21N_T3_DQS_13||align="center"|738.09||align="center"|5||align="center"|360||BANK13 Diff group 1|-| IO_L21P_T3_DQS_13||align="center"|735.9||align="center"|5||align="center"|360||BANK13 Diff group 1|- style="background: gray"| IO_L22N_T3_13||align="center"|969.5||align="center"|5||align="center"|360||BANK13 Diff group 1|- style="background: gray"| IO_L22P_T3_13||align="center"|970.21||align="center"|5||align="center"|360||BANK13 Diff group 1|-|} === FPGA Bank 34 ===
The following table reports the available pins connected to bank 34:
|-
|}
====Routing information====
Routing implemented on Bora SoM allows the use of bank 34's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.
Pairs are highlighted with different colors. When used as differential pairs, differential impedence is 100 Ohm. When used as single-ended signals, impedence is 50 Ohm.
Routing implemented on Bora SoM allows the use of bank 35's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.
Pairs are highlighted with different colors. When used as differential pairs, differential impedence is 100 Ohm. When used as single-ended signals, impedence is 50 Ohm.