Programmable logic (Bora)

Info Box Applies to Bora

Introduction

The following paragraphs describe in detail the available PL I/O pins and how they are routed to the Bora connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, Bora design allows carrier board to power two PL banks in order to achieve complete flexibility in terms of I/O voltage levels too. For more details about PCB design considerations, please refer to the Advanced routing and carrier board design guidelines article.

The following table reports the I/O banks characteristics:

FPGA Bank	I/O Voltage	Voltage Pins	Notes
Bank 35	User defined VIO=FPGA_VDDIO_BANK35 1.8 to 3.3V	J1.2 J1.66 J1.67 J1.68
Bank 34	Fixed VIO=3.3 V	-
Bank 13	User defined VIO=FPGA_VDDIO_BANK13 1.8 to 3.3V	J3.95 J3.96 J3.97 J3.98 J3.99	Bank 13 is available only with Zynq XC7Z020 part number. Although this bank is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pins must not be left open and must be connected anyway, either to ground or to an external I/O voltage.

Each user I/O is labeled IO_LXXY_Tn_ZZZ_ADi_#, where:

• IO indicates a user I/O pin.
• L indicates a differential pair, with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair.
• Tn indicates the memory byte group [0-3]
• ZZZ indicates a MRCC, SRCC or DQS pin
• ADi indicates a XADC (analog-to-digital converter) differential auxiliary analog input [0–15].
• # indicates the bank number.

Highlighted rows are related to signals that are used for particular functions into the SOM.

FPGA Bank 34

The following table reports the available pins connected to bank 34:

Pin Name	Conn. Pin	Notes
IO_0_34	J2.69
IO_25_34	J2.67
IO_L10N_T1_34	J2.65
IO_L10P_T1_34	J2.63
IO_L11N_T1_SRCC_34	J2.59
IO_L11P_T1_SRCC_34	J2.57
IO_L12N_T1_MRCC_34	J2.62
IO_L12P_T1_MRCC_34	J2.60
IO_L13N_T2_MRCC_34	N.A.
IO_L13P_T2_MRCC_34	N.A.
IO_L14N_T2_SRCC_34	J2.56
IO_L14P_T2_SRCC_34	J2.54
IO_L15N_T2_DQS_34	J2.47
IO_L15P_T2_DQS_34	J2.45
IO_L16N_T2_34	J2.50
IO_L16P_T2_34	J2.48
IO_L17N_T2_34	J2.46
IO_L17P_T2_34	J2.44
IO_L18N_T2_34	J2.41
IO_L18P_T2_34	J2.39
IO_L19N_T3_VREF_34	J2.37
IO_L19P_T3_34	J2.35	Internally used as CAN_RX
IO_L1N_T0_34	J2.40
IO_L1P_T0_34	J2.38
IO_L20N_T3_34	J2.36
IO_L20P_T3_34	J2.34
IO_L21N_T3_DQS_34	J2.31
IO_L21P_T3_DQS_34	J2.29
IO_L22N_T3_34	J2.27
IO_L22P_T3_34	J2.25
IO_L23N_T3_34	J2.30
IO_L23P_T3_34	J2.28
IO_L24N_T3_34	J2.26
IO_L24P_T3_34	J2.24
IO_L2N_T0_34	J2.21
IO_L2P_T0_34	J2.19
IO_L3N_T0_DQS_34	J2.17
IO_L3P_T0_DQS_PUDC_B_34	J2.15
IO_L4N_T0_34	J2.20
IO_L4P_T0_34	J2.18
IO_L5N_T0_34	J2.16
IO_L5P_T0_34	J2.14
IO_L6N_T0_VREF_34	J2.11	Internally used for SOM ID. Connected to a 10kΩ pull-up
IO_L6P_T0_34	J2.9	Internally used as CAN_TX
IO_L7N_T1_34	J2.10
IO_L7P_T1_34	J2.8
IO_L8N_T1_34	J2.7	Internally used for SOM ID. Connected to a 10kΩ pull-up
IO_L8P_T1_34	J2.5	Internally used for SOM ID. Connected to a 10kΩ pull-up
IO_L9N_T1_DQS_34	J2.6
IO_L9P_T1_DQS_34	J2.4

Regarding power voltage, take into consideration that Bank 35 is fixed at 3.3V. For routing details, please refer to PL Bank 34 routing.

FPGA Bank 35

The following table reports the available pins connected to bank 35:

Pin Name	Conn. Pin	Notes
IO_0_35	J1.74
IO_25_35	J1.18
IO_L10N_T1_AD11N_35	J1.6
IO_L10P_T1_AD11P_35	J1.5
IO_L11N_T1_SRCC_35	J1.10
IO_L11P_T1_SRCC_35	J1.7
IO_L12N_T1_MRCC_35	J1.27
IO_L12P_T1_MRCC_35	J1.8
IO_L13N_T2_MRCC_35	J1.39
IO_L13P_T2_MRCC_35	J1.40
IO_L14N_T2_AD4N_SRCC_35	J1.36
IO_L14P_T2_AD4P_SRCC_35	J1.34
IO_L15N_T2_DQS_AD12N_35	J1.47
IO_L15P_T2_DQS_AD12P_35	J1.46
IO_L16N_T2_35	J1.44
IO_L16P_T2_35	J1.45
IO_L17N_T2_AD5N_35	J1.37
IO_L17P_T2_AD5P_35	J1.32
IO_L18N_T2_AD13N_35	J1.42
IO_L18P_T2_AD13P_35	J1.43
IO_L19N_T3_VREF_35	J1.64
IO_L19P_T3_35	J1.41
IO_L1N_T0_AD0N_35	J1.53
IO_L1P_T0_AD0P_35	J1.50
IO_L20N_T3_AD6N_35	J1.23
IO_L20P_T3_AD6P_35	J1.21
IO_L21N_T3_DQS_AD14N_35	J1.33
IO_L21P_T3_DQS_AD14P_35	J1.31
IO_L22N_T3_AD7N_35	J1.26
IO_L22P_T3_AD7P_35	J1.25
IO_L23N_T3_35	J1.22
IO_L23P_T3_35	J1.28
IO_L24N_T3_AD15N_35	J1.16
IO_L24P_T3_AD15P_35	J1.20
IO_L2N_T0_AD8N_35	J1.51
IO_L2P_T0_AD8P_35	J1.52
IO_L3N_T0_DQS_AD1N_35	J1.63
IO_L3P_T0_DQS_AD1P_35	J1.61
IO_L4N_T0_35	J1.54
IO_L4P_T0_35	J1.56
IO_L5N_T0_AD9N_35	J1.55
IO_L5P_T0_AD9P_35	J1.57
IO_L6N_T0_VREF_35	J1.62
IO_L6P_T0_35	J1.58
IO_L7N_T1_AD2N_35	J1.11
IO_L7P_T1_AD2P_35	J1.3
IO_L8N_T1_AD10N_35	J1.9
IO_L8P_T1_AD10P_35	J1.12
IO_L9N_T1_DQS_AD3N_35	J1.17
IO_L9P_T1_DQS_AD3P_35	J1.15

On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz. Regarding power voltage, Bank 35 is configurable and must be powered by carrier board. Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog inputs. For routing details, please refer to PL Bank 35 routing.

FPGA Bank 13 (Zynq 7020 only)

N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pins must not be left open and must be connected anyway, either to ground or to an external I/O voltage as described in I/O banks table.

The following table reports the available pins connected to bank 13:

Pin Name	Conn. Pin	Notes
IO_L11N_T1_SRCC_13	J3.136
IO_L11P_T1_SRCC_13	J3.134
IO_L12N_T1_MRCC_13	J3.137
IO_L12P_T1_MRCC_13	J3.135
IO_L13N_T2_MRCC_13	J3.130
IO_L13P_T2_MRCC_13	J3.128
IO_L14N_T2_SRCC_13	J3.131
IO_L14P_T2_SRCC_13	J3.129
IO_L15N_T2_DQS_13	J3.124
IO_L15P_T2_DQS_13	J3.122
IO_L16N_T2_13	J3.125
IO_L16P_T2_13	J3.123
IO_L17N_T2_13	J3.118
IO_L17P_T2_13	J3.116
IO_L18N_T2_13	J3.119
IO_L18P_T2_13	J3.117
IO_L19N_T3_VREF_13	J3.113
IO_L19P_T3_13	J3.111
IO_L20N_T3_13	J3.112
IO_L20P_T3_13	J3.110
IO_L21N_T3_DQS_13	J3.107
IO_L21P_T3_DQS_13	J3.105
IO_L22N_T3_13	J3.106
IO_L22P_T3_13	J3.104
IO_L6N_T0_VREF_13	J3.100

Regarding power voltage, Bank 13 is configurable and must be powered by carrier board. For routing details, please refer to PL Bank 13 routing.