Bureaucrats, dave_user, Administrators
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Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_ADDR class signals. The picture shows connection scheme and the nomenclature used in the table.
[[File:FDDR_ADDR.png|thumb|center|600px]]
Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_CK class signals. The picture shows connection scheme and the nomenclature used in the table.
[[File:FDDR_CK.png|thumb|center|600px]]
{| class="wikitable" border="1"
* place bypass capacitors as close as possible to power balls.
[[File:VREF.png|thumb|center|600px]]
==== Related Xilinx documentation ====
* [http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdf Xilinx Memory Interface Solutions UG586]
