Changes

{{Applies To Bora}}

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The following paragraphs describe in detail the available PL I/O pins and how they are routed to the Bora connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, Bora design allows carrier board to power two PL banks in order to achieve complete flexibility in terms of I/O voltage levels too.

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!FPGA Bank

!I/O Voltage

!Voltage Pins

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|Bank 35

|User defined<br>VIO=FPGA_VDDIO_BANK35<br>'''1.8 to 3.3V'''

|J1.2<br>J1.66<br>J1.67<br>J1.68

|-

|Bank 34

|Fixed<br>'''VIO=3.3 V'''

| -

|-

|Bank 13

|User defined<br>VIO=FPGA_VDDIO_BANK13<br>'''1.8 to 3.3V'''

|J3.95<br>J3.96<br>J3.97<br>J3.98<br>J3.99

Highlighted rows are related to signals that are used for particular functions into the SOM.

The following table reports the available pins connected to bank 34:

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| IO_L3N_T0_DQS_34 || J2.17 ||

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| IO_L4N_T0_34 || J2.20 ||

|-

| IO_L5P_T0_34 || J2.14 ||

|- style="background:#FF6633;"

| IO_L6P_T0_34 || J2.9 || Internally used as CAN_TX

|-

| IO_L7P_T1_34 || J2.8 ||

|-

| IO_L9N_T1_DQS_34 || J2.6 ||

|}

Routing implemented on Bora SoM allows the use of bank 34's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.

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| IO_L14P_T2_SRCC_34||align="center"|1822,02||align="center"|10||align="center"|50||BANK34 xRCC group

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|}

About power voltage, take into consideration that Bank 34 is fixed at 3.3V.

The following table reports the available pins connected to bank 35:

{| class="wikitable" border="1"

On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz. Regarding power voltage, Bank 35 is configurable and must be powered by carrier board. Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog inputs. For routing details, please refer to [[Integration_guide_(Bora)#PL_bank_35 | PL Bank 35 routing]].

On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz.

Signals have been grouped in the following classes:

Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog

inputs.

Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_ADDR class signals. The picture shows connection scheme and the nomenclature used in the table.

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Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_CK class signals. The picture shows connection scheme and the nomenclature used in the table.

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Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_BYTE0 class signals.

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Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_BYTE1 class signals.

[[File:VREF.png|thumb|center|600px]]

* [http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdf Xilinx Memory Interface Solutions UG586]

* [http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ds176_7Series_MIS.pdf Xilinx Memory Interface Solutions Data Sheet]

The following table reports the available pins connected to bank 13:

Regarding power voltage, Bank 13 is configurable and must be powered by carrier board. For routing details, please refer to [[Integration_guide_(Bora)#PL_bank_13_.28XC7Z020_only.29 | PL Bank 13 routing]].

Routing implemented on Bora SoM allows the use of bank 13's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.

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