Difference between revisions of "Programmable logic (BORAXpress)"
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== Introduction == | == Introduction == | ||
| − | The following paragraphs describe in detail the available PL I/O | + | The following paragraphs describe in detail the available PL I/O signals and how they are routed to the BORA Xpress connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, BORA Xpress design allows carrier board to power all three PL banks in order to achieve complete flexibility in terms of I/O voltage levels too. |
| − | For more details about PCB design considerations, please refer to the [[Integration_guide_( | + | For more details about PCB design considerations, please refer to the [[Integration_guide_(Bora/BoraX)#Advanced_routing_and_carrier_board_design_guidelines | Advanced routing and carrier board design guidelines]] article. |
The following table reports the I/O banks characteristics: | The following table reports the I/O banks characteristics: | ||
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!FPGA Bank | !FPGA Bank | ||
| − | !I/O | + | !XC7Z015 |
| − | ! | + | !XC7Z030 |
| − | + | !Bank power supply pins | |
| + | !I/O | ||
| + | !Differentials Pairs | ||
| + | |- | ||
| + | |Bank 13 | ||
| + | |HR | ||
| + | |HR | ||
| + | |J3.95<br>J3.96<br>J3.97<br>J3.98<br>J3.99 | ||
| + | |50 | ||
| + | |24 | ||
| + | |- | ||
| + | |Bank 34 | ||
| + | |HR | ||
| + | |HP | ||
| + | |J2.66<br>J2.68<br>J2.70<br>J2.72 | ||
| + | |50 | ||
| + | |24 | ||
| + | |- | ||
| + | |Bank 35 | ||
| + | |HR | ||
| + | |HP | ||
| + | |J1.2<br>J1.66<br>J1.67<br>J1.68 | ||
| + | |50 | ||
| + | |24 | ||
|- | |- | ||
|} | |} | ||
| + | |||
| + | FPGA I/O Bank definitions: | ||
| + | * '''HR''' = High Range I/O with support for I/O voltage from 1.2V to 3.3V | ||
| + | * '''HP''' = High Performance I/O with support for I/O voltage from 1.2V to 1.8V | ||
Each user I/O is labeled IO_LXXY_Tn_ZZZ_ADi_#, where: | Each user I/O is labeled IO_LXXY_Tn_ZZZ_ADi_#, where: | ||
| Line 27: | Line 54: | ||
* # indicates the bank number. | * # indicates the bank number. | ||
| − | + | Here is a list of FPGA I/O actually used inside BORA Xpress SOM: | |
| − | + | * IO_L6P_T0_34 : CAN_RX | |
| − | + | * IO_L19P_T3_34 : CAN_TX | |
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| − | + | == Routing Information == | |
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| − | + | Routing implemented on Bora Xpress SoM allows the use of MGT serial tranceivers differential pairs ans FPGA's signals as differential pairs as well as single-ended. | |
| − | |||
| − | + | [http://www.dave.eu/sites/default/files/files/BoraX-BoraXEVB-combined-routing.ods This spreadsheet] details routing rules applied to Bora Xpress's signals. Signals are grouped by bank number. The table details also the routing rules of the Bora Xpress SOM combined with Bora Xpress EVB highlighting routing to the FPGA Mezzanine Card (FMC) connector on Bora Xpress EVB. | |
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Introduction[edit | edit source]
The following paragraphs describe in detail the available PL I/O signals and how they are routed to the BORA Xpress connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, BORA Xpress design allows carrier board to power all three PL banks in order to achieve complete flexibility in terms of I/O voltage levels too. For more details about PCB design considerations, please refer to the Advanced routing and carrier board design guidelines article.
The following table reports the I/O banks characteristics:
| FPGA Bank | XC7Z015 | XC7Z030 | Bank power supply pins | I/O | Differentials Pairs |
|---|---|---|---|---|---|
| Bank 13 | HR | HR | J3.95 J3.96 J3.97 J3.98 J3.99 |
50 | 24 |
| Bank 34 | HR | HP | J2.66 J2.68 J2.70 J2.72 |
50 | 24 |
| Bank 35 | HR | HP | J1.2 J1.66 J1.67 J1.68 |
50 | 24 |
FPGA I/O Bank definitions:
- HR = High Range I/O with support for I/O voltage from 1.2V to 3.3V
- HP = High Performance I/O with support for I/O voltage from 1.2V to 1.8V
Each user I/O is labeled IO_LXXY_Tn_ZZZ_ADi_#, where:
- IO indicates a user I/O pin.
- L indicates a differential pair, with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair.
- Tn indicates the memory byte group [0-3]
- ZZZ indicates a MRCC, SRCC or DQS pin
- ADi indicates a XADC (analog-to-digital converter) differential auxiliary analog input [0–15].
- # indicates the bank number.
Here is a list of FPGA I/O actually used inside BORA Xpress SOM:
- IO_L6P_T0_34 : CAN_RX
- IO_L19P_T3_34 : CAN_TX
Routing Information[edit | edit source]
Routing implemented on Bora Xpress SoM allows the use of MGT serial tranceivers differential pairs ans FPGA's signals as differential pairs as well as single-ended.
This spreadsheet details routing rules applied to Bora Xpress's signals. Signals are grouped by bank number. The table details also the routing rules of the Bora Xpress SOM combined with Bora Xpress EVB highlighting routing to the FPGA Mezzanine Card (FMC) connector on Bora Xpress EVB.
