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Processor and memory subsystem (BoraLite)

41 bytes added, 15:33, 23 February 2021
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{{Applies To BoraLite}}
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= Processor and memory subsystem =
All interface signals Bora provides are routed through a 204 pin DDR3 SO-DIMM edge connector (named J1). The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA Lite pinout specifications.
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