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→NOR flash bank
{{Applies To BoraLite}}
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== Processor and memory subsystem ==
{| class="wikitable" |
| align="center" style="background:#f0f0f0;" align="center"|'''Processor'''| align="center" style="background:#f0f0f0;" align="center"|'''Programmable logic cells'''| align="center" style="background:#f0f0f0;" align="center"|'''LUTs'''| align="center" style="background:#f0f0f0;" align="center"|'''Flip flops'''| align="center" style="background:#f0f0f0;" align="center"|'''Extensible block RAM'''| align="center" style="background:#f0f0f0;" align="center"|'''DSP slices'''| align="center" style="background:#f0f0f0;" align="center"|'''Peak DSP performance'''
|-
| XC7Z007S ||23K Logic Cells ||14400 ||28800 ||1.8 Mb ||66 ||73 GMACs
| XC7Z020 ||85K Logic Cells ||53200 ||106400 ||4.9 Mb ||220 ||276 GMACs
|-
|+ align="bottom" style="caption-side: bottom" align="bottom" | Table: XC7-Z0xx comparison
|}
| '''Size min'''||8 MB
|-
| '''Size max'''||16 MB - The limitation to max 16MB is due to this [https://support.xilinx.com/s/article/57744?language=en_US Errata from Xilinx]. The proposed solution by Xilinx has not been approved by DAVE Embedded Systems
|-
| '''Chip select'''||SPI_CS0n
All interface signals Bora provides are routed through a 204 pin DDR3 SO-DIMM edge connector (named J1). The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA Lite pinout specifications.
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