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{{Applies To BoraLite}}
{{InfoBoxBottom}}
<section begin="Body" />== Processor and memory subsystem ==
The heart of BORA Lite module is composed of the following components:
This chapter shortly describes the main BORA Lite components.
=== Processor Info ===
The Zynq™-7000 family is based on the Xilinx Extensible Processing Platform (EPP) architecture. These products integrate a feature-rich single/dual core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces.
{| class="wikitable" |
| align="center" style="background:#f0f0f0;" align="center"|'''Processor'''| align="center" style="background:#f0f0f0;" align="center"|'''Programmable logic cells'''| align="center" style="background:#f0f0f0;" align="center"|'''LUTs'''| align="center" style="background:#f0f0f0;" align="center"|'''Flip flops'''| align="center" style="background:#f0f0f0;" align="center"|'''Extensible block RAM'''| align="center" style="background:#f0f0f0;" align="center"|'''DSP slices'''| align="center" style="background:#f0f0f0;" align="center"|'''Peak DSP performance'''
|-
| XC7Z007S ||23K Logic Cells ||14400 ||28800 ||1.8 Mb ||66 ||73 GMACs
| XC7Z020 ||85K Logic Cells ||53200 ||106400 ||4.9 Mb ||220 ||276 GMACs
|-
|+ align="bottom" style="caption-side: bottom" align="bottom" | Table: XC7-Z0xx comparison
|}
=== RAM memory bank ===
DDR3 SDRAM memory bank is composed by 2x 16-bit width chips resulting in a 32-bit combined width bank. The following table reports the SDRAM specifications:
|}
=== NOR flash bank ===
NOR flash is a Serial Peripheral Interface (SPI) device. By default this device is connected to SPI channel 0 and acts as boot memory. The following table reports the NOR flash specifications:
| '''Size min'''||8 MB
|-
| '''Size max'''||16 MB - The limitation to max 16MB is due to this [https://support.xilinx.com/s/article/57744?language=en_US Errata from Xilinx]. The proposed solution by Xilinx has not been approved by DAVE Embedded Systems
|-
| '''Chip select'''||SPI_CS0n
|}
=== NAND flash bank ===
On board main storage memory is a 8-bit wide NAND flash. By default it is connected to chip select. The following table reports the NAND flash specifications:
|}
=== Power supply unit ===
Bora, as the other Ultra Line CPU modules, embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters. For detailed information, please refer to the [[Power_BORA_Lite_SOM/BORA_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(BoraPSU)_and_recommended_power-up_sequence | Power supply]]wiki page.
=== CPU module connectors ===
All interface signals Bora provides are routed through a 204 pin DDR3 SO-DIMM edge connector (named J1). The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA Lite pinout specifications.
<section end="Body" />
