View source for Processor and memory subsystem (BoraLite)

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== Processor and memory subsystem ==

The heart of BORA Lite module is composed of the following components:
* Xilinx Zynq XC7Z007S/012S/014S single core ARM Cortex-A9 or XC7Z010/XC7Z020 dual core ARM Cortex-A9 MPCore
* Power supply unit
* DDR memory banks
* NOR and NAND flash banks
* 204 SO-DIMM connector with interfaces signals

This chapter shortly describes the main BORA Lite components.

=== Processor Info ===

The Zynq™-7000 family is based on the Xilinx Extensible Processing Platform (EPP) architecture. These products integrate a feature-rich single/dual core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces.
The Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing performance, power, and ease of use typically associated with ASIC and ASSPs. The range of devices in the Zynq-7000 AP SoC family enables designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools. While each device in the Zynq-7000 family contains the same PS, the PL and I/O resources vary between the devices. As a result, the Zynq-7000 AP SoC devices are able to serve a wide range of applications including:
* Automotive driver assistance, driver information, and infotainment
* Broadcast camera
* Industrial motor control, industrial networking, and machine vision
* IP and Smart camera
* LTE radio and baseband
* Medical diagnostics and imaging
* Multifunction printers
* Video and night vision equipment

The processors in the PS always boot first, allowing a software centric approach for PL system boot and PL configuration. The PL can be configured as part of the boot process or configured at some point in the future. Additionally, the PL can be completely reconfigured or used with partial, dynamic reconfiguration (PR). PR allows configuration of a portion of the PL. This enables optional design changes such as updating coefficients or time-multiplexing of the PL resources by swapping in new algorithms as needed.

Bora can mount two versions of the Zynq processor. The following table shows a comparison between the processor models, highlighting the differences:

{| class="wikitable" | 
| style="background:#f0f0f0;" align="center" |'''Processor'''
| style="background:#f0f0f0;" align="center" |'''Programmable logic cells'''
| style="background:#f0f0f0;" align="center" |'''LUTs'''
| style="background:#f0f0f0;" align="center" |'''Flip flops'''
| style="background:#f0f0f0;" align="center" |'''Extensible block RAM'''
| style="background:#f0f0f0;" align="center" |'''DSP slices'''
| style="background:#f0f0f0;" align="center" |'''Peak DSP performance'''
|-
| XC7Z007S ||23K Logic Cells ||14400 ||28800 ||1.8 Mb ||66 ||73 GMACs
|-
| XC7Z012S ||55K Logic Cells ||34400 ||68800 ||2.5 Mb ||120 ||131 GMACs
|-
| XC7Z014S ||65K Logic Cells ||40600 ||81200 ||3.8Mb ||170 ||187 GMACs
|-
| XC7Z010 ||28K Logic Cells ||17600 ||35200 ||2.1 Mb ||80 ||100 GMACs
|-
| XC7Z020 ||85K Logic Cells ||53200 ||106400 ||4.9 Mb ||220 ||276 GMACs
|-
|+ style="caption-side: bottom" align="bottom" | Table: XC7-Z0xx comparison
|}

=== RAM memory bank ===

DDR3 SDRAM memory bank is composed by 2x 16-bit width chips resulting in a 32-bit combined width bank. The following table reports the SDRAM specifications:

{| class="wikitable" | 
|-
| '''CPU connection'''||SDRAM bus 
|-
| '''Size min'''||512 MB 
|-
| '''Size max'''||1 GB 
|-
| '''Width'''||32 bit 
|-
| '''Speed'''||533 MHz 
|-
|}

=== NOR flash bank ===

NOR flash is a Serial Peripheral Interface (SPI) device. By default this device is connected to SPI channel 0 and acts as boot memory. The following table reports the NOR flash specifications:

{| class="wikitable" | 
|-
| '''CPU connection'''||SPI Channel 0
|-
| '''Size min'''||8 MB 
|-
| '''Size max'''||16 MB - The limitation to max 16MB is due to this [https://support.xilinx.com/s/article/57744?language=en_US Errata from Xilinx]. The proposed solution by Xilinx has not been approved by DAVE Embedded Systems 
|-
| '''Chip select'''||SPI_CS0n
|-
| '''Bootable'''||Yes
|-
|}

=== NAND flash bank ===

On board main storage memory is a 8-bit wide NAND flash. By default it is connected to  chip select. The following table reports the NAND flash specifications:

{| class="wikitable" | 
|-
| '''CPU connection'''||Static memory controller 
|-
| '''Page size'''|| 512 byte, 2 kbyte or 4 kbyte
|-
| '''Size min'''||128 MB 
|-
| '''Size max'''||1 GB 
|-
| '''Width'''||8 bit 
|-
| '''Chip select'''||NAND_CS0
|-
| '''Bootable'''||Yes 
|-
|}

=== Power supply unit ===

Bora, as the other Ultra Line CPU modules, embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters. For detailed information, please refer to the [[BORA_Lite_SOM/BORA_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power supply]] wiki page.

=== CPU module connectors ===

All interface signals Bora provides are routed through a 204 pin DDR3 SO-DIMM edge connector (named J1). The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA Lite pinout specifications.
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