{{InfoBoxBottom}}

The heart of Bora Xpress module is composed of the following components:

This chapter shortly describes the main Bora Xpress components.

The Zynq™-7000 family is based on the Xilinx Extensible Processing Platform (EPP) architecture. These products integrate a feature-rich dual-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces.

The processors in the PS always boot first, allowing a software centric approach for PL system boot and PL configuration. The PL can be configured as part of the boot process or configured at some point in the future. Additionally, the PL can be completely reconfigured or used with partial, dynamic reconfiguration (PR). PR allows configuration of a portion of the PL. This enables optional design changes such as updating coefficients or time-multiplexing of the PL resources by swapping in new algorithms as needed.

{| class="wikitable" |

|-

| XC7Z015 ||74K Logic Cells ||46200 ||92400 ||3.3 Mb ||160 ||200 GMACs ||GTP (4 Lanes)||6.25 Gb/s

| XC7Z030 ||125K Logic Cells ||78600 ||157200 ||9.3 Mb ||400 ||593 GMACs||GTX (4 Lanes)||6.6 Gb/s

|-

|}

DDR3 SDRAM memory bank is composed by 2x 16-bit width chips resulting in a 32-bit combined width bank. The following table reports the SDRAM specifications:

|}

NOR flash is a Serial Peripheral Interface (SPI) device. By default this device is connected to SPI channel 0 and acts as boot memory. The following table reports the NOR flash specifications:

| '''Size min'''||8 MB

|-

|-

| '''Chip select'''||SPI_CS0n

|}

On board main storage memory is a 8-bit wide NAND flash. By default it is connected to chip select. The following table reports the NAND flash specifications:

|}