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→Quad-SPI
=== Quad-SPI ===
Quad-SPI is used to access multi-bit serial flash memory devices for high throughput and low pin count applications. The controller operates in one of three modes: I/O mode, linear addressing mode, and legacy SPI mode. The following table describes the interface signals:
{| class="wikitable"
!Notes
|-
|NAND_CS0 SPI0_CS0 || J1.122 120 || NAND flash chip Chip select 0 || MIO bank 0, pin 01
|-
|NAND_IO0 SPI0_CS1 || J1.119 122 || NAND I/O 0 Chip select 1 || MIO bank 0, pin 50
|-
|NAND_IO1 SPI0_DQ0 || J1.129 125 || NAND 1-bit: Master Output<br>2-bit: I/O0<br>4-bit: I/O 1 O0 || MIO bank 0, pin 62
|-
|NAND_IO2 SPI0_DQ1 || J1.121 123 || NAND 1-bit: Master Input<br>2-bit: I/O1<br>4-bit: I/O 2 O1 || MIO bank 0, pin 43
|-
|NAND_IO3 SPI0_DQ2 || J1.124 121 || NAND I/O 3 || MIO bank 0, pin 13|1-bit: Write protect<br>2-|NAND_IO4 || J1.126 || NAND I/O bit: Write protect<br>4 || MIO bank 0, pin 9|-|NAND_IO5 || J1.128 || NAND I/O 5 || MIO bank 0, pin 10|-|NAND_IO6 || J1.132 || NAND bit: I/O 6 O0 || MIO bank 0, pin 11|-|NAND_IO7 || J1.134 || NAND I/O 7 || MIO bank 0, pin 12|-|NAND_WE || J1.123 || NAND write enable || MIO bank 0, pin 3|-|NAND_ALE || J1.125 || NAND address latch || MIO bank 0, pin 2|-|NAND_RB || J1.136 || NAND ready/busy || MIO bank 0, pin 8|-|NAND_CLE || J1.138 || NAND command latch enable || MIO bank 0, pin 74
|-
|}