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== Notes on pin assignment ==
For detailed information on MIO and EMIO configuration, please refer to section 2.5.1 /“I/O Peripheral (IOP) Interface Routing”) of the Zynq-7000 Technical Reference Manual.On the Bora Xpress SOM, the MIO module is configured for providing a standard set of peripherals (eg, Ethernet, USB, …); some pins of the EMIO are also used to implement some functions (eg: I2C, specific I/Os). Plese refer to the following sections for detailed information.
== PS interfaces ==
The 54 pins of the MIO module are assigned as reported in the following table:
{| class="wikitable"
|-
!MIO Pins
!Function
|-
|MIO[0:14]
|Quad-SPI and NAND flash
|-
|MIO[15]
|EX_WDT_REARM (watchdog WDI)<br>Optionally, it can act as SWDT reset out
|-
|MIO[16:27]
|Gigabit Ethernet
|-
|MIO[28:39]
|USB On-The-Go
|-
|MIO[40:45]
|SD/SDIO/MMC
|-
|MIO[46:47]
|I²C0
|-
|MIO[48:49]
|UART1
|-
|MIO[52]
|Ethernet Management Data Clock input
|-
|MIO[53]
|Ethernet Management Data Input/Output
|-
|}
=== Gigabit Ethernet ===
On-board Ethernet PHY (Micrel KSZ9031RNX) provides interface signals required to implement the 10/100/1000 Mbps Ethernet port. The transceiver is connected to the Gigabit Ethernet Controller (GEM) through RGMII interface on MIO bank 1, pins PS_MIO[16:27]. For further details (eg: connection and selection of the magnetics), please refer to the Micrel KSZ9031RNX datasheet. The following table describes the interface signals:
{| class="wikitable"
|-
!Pin name
!Conn. pin
!Function
!Notes
|-
|ETH_TXRX0_P || J1.105 || Media Dependent Interface[0], positive pin || -
|-
|ETH_TXRX0_M || J1.103 || Media Dependent Interface[0], negative pin || -
|-
|ETH_TXRX1_P || J1.99 || Media Dependent Interface[1], positive pin || -
|-
|ETH_TXRX1_M || J1.97 || Media Dependent Interface[1], negative pin || -
|-
|ETH_TXRX2_P || J1.102 || Media Dependent Interface[2], positive pin || -
|-
|ETH_TXRX2_M || J1.100 || Media Dependent Interface[2], negative pin || -
|-
|ETH_TXRX3_P || J1.96 || Media Dependent Interface[3], positive pin || -
|-
|ETH_TXRX3_M || J1.94 || Media Dependent Interface[3], negative pin || -
|-
|ETH_MDIO || J1.87 || Management Data Input/Output || -
|-
|ETH_MDC || J1.89 || Management Data Clock input || -
|-
|ETH_LED1 || J1.91 || Activity LED || -
|-
|ETH_LED2 || J1.93 || Link LED || -
|-
|DVDDH || J1.107 || 1.8V digital VDD_I/O of Ethernet PHY || -
|-
|}
=== USB ===
Bora provides one USB 2.0 (Full Speed, up to 480 Mbps) port with on-board PHY (SMSC USB3317) and support to the On-The-Go (OTG) specifications. The transceiver is connected to the USB1 controller (MIO bank 1, pins PS_MIO[28:39]). The following table describes the interface signals:
{| class="wikitable"
|-
!Pin name
!Conn. pin
!Function
!Notes
|-
|USBP1 || J1.114 || D+ pin of the USB cable || -
|-
|USBM1 || J1.116 || D- pin of the USB cable || -
|-
|USBOTG_CPEN || J1.111 || External 5 volt supply enable || This pin is used to enable the external Vbus power supply
|-
|OTG_VBUS || J1.113 || VBUS pin of the USB cable || -
|-
|OTG_ID || J1.115 || ID pin of the USB cable || For non-OTG applications this pin can be floated. For an A-device ID is grounded. For a B-device ID is floated.
|-
|}
=== Quad-SPI ===
Quad-SPI is used to access multi-bit serial flash memory devices for high throughput and low pin count applications. The controller operates in one of three modes: I/O mode, linear addressing mode, and legacy SPI mode. The following table describes the interface signals:
{| class="wikitable"
|-
!Pin name
!Conn. pin
!Function
!Notes
|-
|SPI0_CS0 || J1.120 || Chip select 0 || MIO bank 0, pin 1
|-
|SPI0_CS1 || J1.122 || Chip select 1 || MIO bank 0, pin 0
|-
|SPI0_DQ0 || J1.125 || 1-bit: Master Output<br>2-bit: I/O0<br>4-bit: I/O0 || MIO bank 0, pin 2
|-
|SPI0_DQ1 || J1.123 || 1-bit: Master Input<br>2-bit: I/O1<br>4-bit: I/O1 || MIO bank 0, pin 3
|-
|SPI0_DQ2 || J1.121 || 1-bit: Write protect<br>2-bit: Write protect<br>4-bit: I/O0 || MIO bank 0, pin 4
|-
|SPI0_DQ3 || J1.119 || 1-bit: Hold<br>2-bit: Hold<br>4-bit: I/O3 || MIO bank 0, pin 5
|-
|SPI0_SCLK || J1.129 || Serial clock || MIO bank 0, pin 6
|-
|}
=== Static memory controller ===
Static memory controller (SMC) signals are routed to the connectors to connect an external flash NAND memory chip. The following table describes the interface signals:
{| class="wikitable"
|-
!Pin name
!Conn. pin
!Function
!Notes
|-
|NAND_CS0 || J1.122 || NAND flash chip select || MIO bank 0, pin 0
|-
|NAND_IO0 || J1.119 || NAND I/O 0 || MIO bank 0, pin 5
|-
|NAND_IO1 || J1.129 || NAND I/O 1 || MIO bank 0, pin 6
|-
|NAND_IO2 || J1.121 || NAND I/O 2 || MIO bank 0, pin 4
|-
|NAND_IO3 || J1.124 || NAND I/O 3 || MIO bank 0, pin 13
|-
|NAND_IO4 || J1.126 || NAND I/O 4 || MIO bank 0, pin 9
|-
|NAND_IO5 || J1.128 || NAND I/O 5 || MIO bank 0, pin 10
|-
|NAND_IO6 || J1.132 || NAND I/O 6 || MIO bank 0, pin 11
|-
|NAND_IO7 || J1.134 || NAND I/O 7 || MIO bank 0, pin 12
|-
|NAND_WE || J1.123 || NAND write enable || MIO bank 0, pin 3
|-
|NAND_ALE || J1.125 || NAND address latch || MIO bank 0, pin 2
|-
|NAND_RB || J1.136 || NAND ready/busy || MIO bank 0, pin 8
|-
|NAND_CLE || J1.138 || NAND command latch enable || MIO bank 0, pin 7
|-
|}
=== I²C0 ===
This I²C module is a bus controller that can function as a master or a slave in a multi-master design. It supports an extremely wide clock frequency range up to 400 Kb/s. I²C0 is internally connected to the following devices:
* [[Thermal IC (BoraXpress)|Thermal IC]]: Texas Instruments TMP421 (Address: 0x4F)
* [[RTC (BoraXpress)|RTC]]: Maxim Integrated DS3232 (Address: 0x68)
The following table describes the interface signals:
{| class="wikitable"
|-
!Pin name
!Conn. pin
!Function
!Notes
|-
|PS_I2C0_CK || J1.88 || I2C clock || -
|-
|PS_I2C0_DAT || J1.84 || I2C data || -
|-
|}
=== SD/SDIO ===
The SD/SDIO controller controller is compatible with the standard SD Host Controller Specification Version 2.0
Part A2. The core also supports up to seven functions in SD1, SD4, but does not support SPI mode. It does support SD high-speed (SDHS) and SD High Capacity (SDHC) card standards. The SD/SDIO controller also supports MMC3.31.
The following table describes the interface signals:
{| class="wikitable"
|-
!Pin name
!Conn. pin
!Function
!Notes
|-
|PS_SD0_CLOCK || J1.85 || SD/SDIO/MMC clock || -
|-
|PS_SD0_CMD || J1.81 || SD/SDIO/MMC command || -
|-
|PS_SD0_DAT0 || J1.79 || SD/SDIO/MMC data 0 || -
|-
|PS_SD0_DAT1 || J1.77 || SD/SDIO/MMC data 1 || -
|-
|PS_SD0_DAT2 || J1.75 || SD/SDIO/MMC data 2 || -
|-
|PS_SD0_DAT3 || J1.73 || SD/SDIO/MMC data 3 || -
|-
|}
=== UART1 ===
The UART controller is a full-duplex asynchronous receiver and transmitter that supports a wide range of programmable baud rates and I/O signal formats. UART1 port is routed to the SOM connectors as a 2-wire interface. The following table describes the interface signals:
{| class="wikitable"
|-
!Pin name
!Conn. pin
!Function
!Notes
|-
|PS_UART1_RX || J1.80 || UART Receive line || -
|-
|PS_UART1_TX || J1.82 || UART Transmit line || -
|-
|}
=== CAN ===
CAN port is connected to on-board transceiver (TI SN65HVD232) which converts the single-ended CAN signals of the controller to the differential signals of the physical layer. The following table describes the interface signals:
{| class="wikitable"
|-
!Pin name
!Conn. pin
!Function
!Notes
|-
|CAN_H || J2.107 || High bus output || -
|-
|CAN_L || J2.105 || Low bus output || -
|-
|}
Optionally, the on-board PHY can be excluded (for example, to use an external PHY on the carrier board) and the single-ended CAN signals are routed to the connectors. The following table describes the interface signals:
{| class="wikitable"
|-
!Pin name
!Conn. pin
!Function
!Notes
|-
|CAN_RX || J2.35 || Receive data pin || Routed to EMIO (pin IO_L19P_T3_34)
|-
|CAN_TX || J2.9 || Transmit data pin || Routed to EMIO (pin IO_L6P_T0_34)
|-
|}
Please contact our Sales Department for more information about this hardware option.
=== JTAG ===
The Zynq-7000 family of AP SoC devices provides debug access via a standard JTAG (IEEE 1149.1) debug interface. This JTAG port grants access to the device chain composed of both the CPU core and the FPGA part. The following table describes the interface signals:
{| class="wikitable"
|-
!Pin name
!Conn. pin
!Function
!Notes
|-
|JTAG_TDO || J2.80 || JTAG TDO || -
|-
|JTAG_TDI || J2.82 || JTAG TDI || -
|-
|JTAG_TMS || J2.84 || JTAG TMS || -
|-
|JTAG_TCK || J2.86 || JTAG TCK || -
|-
|}