Changes

Following sections show some examples of the effects of such scheme.

==Interrupt latency==

In some cases, high interrupt latencies can cause "visible" effects that may be hard to explain at first sight. Typical example refers to the RX channel of UART ports. When receiving data stream rate is relatively high with respect to the RX FIFO size, it is strongly recommended to implement hardware flow control signals (RTS/CTS) in order to prevent well-known FIFO overrun condition (see also [https://community.freescale.com/thread/349117 this page]). In case hardware flow control is not available, FIFO overrun may be experienced. The probability of this event is proportional to the UART interrupt latency: the greater the latency, the more probable is the occurrence of FIFO overrun and thus the loss of received data. FIFO overrun event is usually reported by kernel by printing this message on console:

* internal LDOs-based: in this case processor's internal linear regulators are used to change such voltages.

PMIC is connected to the processor via I2C bus. As such, every time a transaction is needed, several I2C packets need to be trasnmitted over I2C bus, resulting in a relatively slow overall transaction time. In case LDOs-based approach is adopted instead, transaction are quicker because LDOs configuration registers are directly accessible in the processor's address space. On the other hand, the use of LDOs has significant drawback as explained in the following section.

==Processor heating and lifetime==

Use of internal LDOs increases the power dissipation on processor side significantly. As a consequence, operating junction temperature increases as well. This fact has to be taken into consideration at system integration level, as it affects directly expected processor lifetime. For more details please refer to

and

<ref name="AN4725">Freescale Semiconductor, Inc., ''AN4725 i.MX 6Solo/6DualLite Product Lifetime Usage Estimates''</ref>.