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→Power Supply Unit (PSU) and recommended power-up sequence
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== Power Supply Unit (PSU) and recommended power-up sequence ==
Implementing correct power-up sequence for Zynq-based system is not a trivial task because several power rails are involved. Bora /BORA Lite SOM simplifies this task and embeds all the needed circuitry. The following picture shows a simplified block diagram of power supply subsystem.
[[File:Bora-power-sequence.png|thumb|center|600px|Bora Simplified block diagram of recommended power scheme]][[File:BoraLite-power-sequence1.jpg|thumb|center|600px|BORA Lite Simplified block diagram of recommended power scheme]]
The recommended power-up sequence is:
Bora's PSU is designed to be robust against misbehaving power rails. However, the recommended power-on ramp for core and I/O supplies ranges from 1 to 6 V/ms.
'''N.B.''': Regarding power off, it is recommended taht that I/O supply is turned off before core supply. (1) For BORA SOM this step is not mandatory and CB_PWR_GOOD can be left floating. CB_PWR_GOOD is provided to prevent, if necessary, BORA's PSU to turn on during ramp of carrier board 3.3VIN rail. Depending on carrier board's PSU design, this may lead to undesired glitches during ramp-up.
=== XCN15034 and power-off sequence ===
On 29th September 2015 Xilinx released a Product Change Notice indicating new power on/off requirements about Zynq components.
A specific analysis has been undertaken with the help of Xilinx technical support to verify the compliance of Bora with respect to the new requirements. This activity has led to the following recommendation: in order to prevent situations that might not fulfill such requirements, 3.3VIN off ramp speed must not exceed 50 V/mss.
For more details about this matter, please refer to AR #65240<ref name="AR65240">http://www.xilinx.com/support/answers/65240.html</ref> and XCN15034<ref name="XCN15034">http://www.xilinx.com/support/documentation/customer_notices/xcn15034.pdf</ref>.
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