Power (AxelUltra)

Info Box Applies to Axel Ultra

Power Supply Unit (PSU) and recommended power-up sequence

Implementing correct power-up sequence for i.MX6 processors is not a trivial task because several power rails are involved. Axel SOM simplifies this task and embeds all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:

The PSU is composed of two main blocks:

• power management integrated circuit (PMIC, Freescale PF0100E0 - on request this part is available in automotive grade)
• additional generic power management circuitry that completes PMIC functionalities.

The PSU:

• generates the proper power-up sequence required by i.MX processor and surrounding memories and peripherals
• synchronizes the powering up of carrier board in order to prevent back power
• provides some spare regulated voltages that can be used to power carrier board devices

Power-up sequence

The typical power-up sequence is the following:

1. (optional) PMIC_LICELL is powered
   (optional) RTC_VBAT is powered
2. 2V8-4V5 main power supply rail is powered
3. CPU_PORn (active-low) is driven low
4. PMIC activates PMIC_VSNVS power output
5. PMIC_PWRON signal is pulled-up (unless carrier board circuitry keeps this signal low for any reason)
6. PMIC transitions from OFF to ON state
7. PMIC initiates power-up sequence needed by MX6 processor
8. NVCC_AXEL_I/O_3.3V/1.8V signal is raised; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa).
9. configurable I/O power rails (NVCC_CSI_EXT, NVCC_EIM_EXT, NVCC_SD3_EXT, NVCC_LCD_EXT) are powered by carrier board
10. PMIC VGEN6 LDO is turned on (this is the last regulator turned on automatically by PMIC)
11. CPU_PORn is released.

Power rails and related signals

The following list describes in detail the power rails and the power related signals. Please note that PMIC regulators ouput voltages can be changed only if explicitly allowed.

• 2V8-4V5: this is external main power rail. Voltage range is 2.8 - 4.5V
• PMIC_CELL: PMIC's coin cell supply input/output
• RTC_VBAT: this rail is connected to pin 6 of Maxim DS3232MZ+ RTC
• NVCC_CSI_EXT: this rail powers MX6's NVCC_CSI domain
• NVCC_EIM_EXT: this rail powers MX6's NVCC_EIM0, NVCC_EIM1 and NVCC_EIM2 domains
• NVCC_SD3_EXT: this rail powers MX6's NVCC_SD3 domain
• NVCC_LCD_EXT: this rail powers MX6's NVCC_LCD domain
• NVCC_AXEL_I/O_3.3V/1.8V: this output signal is used to indicate when carrier board's circuitry interfacing Axel's I/Os has to be powered up. Proper usage of this pin requires to connect it to an AND port together with the PMIC_PWRON signal, wiring the output of the port to the enable pin of the switch mounted on the carrier board. This interconnect is necessary because deasserting the PMIC_PWRON signal is not sufficient to properly reset all the PMIC power voltages.
• VGEN1: PMIC's VGEN1 regulator output; this regulator is not used by any Axel's internal load. Output voltage can be selected by user.
• VGEN2: PMIC's VGEN2 regulator output; this regulator is not used by any Axel's internal load. Output voltage can be selected by user.
• VGEN4_1V8: PMIC's VGEN4 regulator output; output voltage (1.8V) must not be altered. Up to 150mA can be drawn.
• VGEN6: PMIC's VGEN6 regulator output; this regulator is not used by any Axel's internal load. Output voltage can be selected by user.
• SW4_xV/1.8V: PMIC's SW4 regulator output voltage (1.8V). This voltage must not be altered. Up to 500mA can be drawn.
• PMIC_VSNVS: PMIC's LDO or coin cell output to processor. Please refer to PMIC's datasheet for current limit. Please take into account internal loads as depicted in Axel reset scheme picture.
• PMIC_SWBST_SUPPLY: this rail is connected to PMIC's SWBSTIN pad and can be used to power SWBST boost regulator. This regulator is not used by any Axel's internal load. Output voltage can be selected by user.
• PMIC_5V: this is output of SWBST boost regulator. This regulator is not used by any Axel's internal load. Output voltage can be selected by user.
• VDDCORE, VDDSOC, DDR_1V5, 1V2_ETH, VDDHIGH_VPH, VDDSOC_CAP, VDDPU, VDD_ARM23_CAP, VDD_ARM01_CAP, VDGEN5_2V8, VDD_BUS_CAP, VDD_SNVS_CAP, VGEN3_2V5, NVCC_PLL_OUT: these signals route power voltage generated by Axel PSU. These optional signals (in the default configuration, the pins are dedicated to other functions ) are meant to enable monitoring of internal voltages by carrier board circuitry. For further details, please refer to pinout table.

For further details, please refer to the PMIC documentation: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MMPF0100%7CPF0100