View source for Power (AxelUltra)

=== Power rails and related signals ===

The following list describes in detail the power rails and the power related signals. Please note that PMIC regulators ouput voltages can be changed only if explicitly allowed.

* 2V8-4V5: this is external main power rail. Voltage range is 2.8 - 4.5V
* PMIC_CELL: PMIC's coin cell supply input/output
* RTC_VBAT: this rail is connected to pin 6 of Maxim DS3232MZ+ RTC
* NVCC_CSI_EXT: this rail powers MX6's NVCC_CSI domain
* NVCC_EIM_EXT: this rail powers MX6's NVCC_EIM0, NVCC_EIM1 and NVCC_EIM2 domains
* NVCC_SD3_EXT: this rail powers MX6's NVCC_SD3 domain
* NVCC_LCD_EXT: this rail powers MX6's NVCC_LCD domain
* NVCC_AXEL_I/O_3.3V/1.8V: this output signal is used to indicate when carrier board's circuitry interfacing Axel's I/Os has to be powered up. 
* VGEN1: PMIC's VGEN1 regulator output; this regulator is not used by any Axel's internal load. Output voltage can be selected by user.
* VGEN2: PMIC's VGEN2 regulator output; this regulator is not used by any Axel's internal load. Output voltage can be selected by user.
* VGEN4_1V8: PMIC's VGEN4 regulator output; output voltage (1.8V) must not be altered. Up to 150mA can be drawn.
* VGEN6: PMIC's VGEN6 regulator output; this regulator is not used by any Axel's internal load. Output voltage can be selected by user.
* SW4_xV/1.8V: PMIC's SW4 regulator output voltage (1.8V). This voltage must not be altered. Up to 500mA can be drawn.
* PMIC_VSNVS: PMIC's LDO or coin cell output to processor. Please refer to PMIC's datasheet for current limit. Please take into account internal loads as depicted in Axel reset scheme picture.
* PMIC_SWBST_SUPPLY: this rail is connected to PMIC's SWBSTIN pad and can be used to power SWBST boost regulator. This regulator is not used by any Axel's internal load. Output voltage can be selected by user.
* PMIC_5V: this is output of SWBST boost regulator. This regulator is not used by any Axel's internal load. Output voltage can be selected by user.
* VDDCORE, VDDSOC, DDR_1V5, 1V2_ETH, VDDHIGH_VPH, VDDSOC_CAP, VDDPU, VDD_ARM23_CAP, VDD_ARM01_CAP, VDGEN5_2V8, VDD_BUS_CAP, VDD_SNVS_CAP, VGEN3_2V5, NVCC_PLL_OUT: these signals route power voltage generated by Axel PSU. These optional signals (in the default configuration, the pins are dedicated to other functions ) are meant to enable monitoring of internal voltages by carrier board circuitry. For further details, please refer to pinout table.

For further details, please refer to the PMIC documentation: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MMPF0100%7CPF0100