3,260
edits
Changes
→J2 odd pins (1 to 139)
|}
==J2 odd even pins (1 2 to 139140)==
{| class="wikitable" {{table}}
| align="center" style="background:#f0f0f0;"|'''Pin'''
| J2.60||VIN[0]B_CLK/GP1[9]||CPU.VIN[0]B_CLK/CLKOUT0/GP1[9]||AE17||||I/O||||(1)
|-
| J2.60||VRTC||MTR||-||||O||||(1)
|-
| J2.62||VOUT0_R_CR2/GP2_26||CPU.VOUT[0]_R_CR[2]/EMU4/GP2[26]||AD9||||I/O||||(1)
|-
| J2.62||PLL_1V8||MTR||-||||O||||(1)
|-
| J2.64||VOUT0_R_CR3/GP2_27||CPU.VOUT[0]_R_CR[3]/GP2[27]||AB9||||I/O||||(1)
|-
| J2.64||CORE_VDD||MTR||-||||O||||(1)
|-
| J2.66||"VOUT1_G_Y_YC3GP3_23||CPU.EMAC[0]_MTCLK/GP3_7VIN[1]B_D[0]/SPI[3]_SCS[3]n/I2C[2]_SDA/GP3[23]||L24||||I/O||||(1)
|-
| GP3_23"J2.66||VOUT1_G_Y_YC3/GP3_7||"CPU.VOUT[1]_G_Y_YC[3]/EMAC[1]_MRXD[6]/VIN[1]A_D[8]/GP3[7] (||Y23)||||||||
|-
| EMAC[0]_MTCLK/VIN[1]B_D[0]/SPI[3]_SCS[3]n/I2C[2]_SDA/GP3[23]"||L24||||I/O||||(1)|-| J2.66||CVDD_ARM||MTR||-||||O||||(1)
|-
| J2.68||VOUT1_R_CR9/GP3_19||CPU.VOUT[1]_R_CR[9]/EMAC[1]_MTXEN/VIN[1]A_D[20]/PATA_D[12]/UART5_TXD/GP3[19]||Y24||||I/O||||