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** Voltage: I/O voltage levels
→J2 odd pins (1 to 139)
** G = Ground
** A = Analog signal
The Internal connection column reports the name of the microprocessor signal, which in turn contains references to all the peripheral functions that can be associated to that pin. For example, the following pin name <code>CPU.VOUT[1]_B_CB_C[4]/EMAC[1]_MRXD[0]/VIN[1]A_D[1]/UART4_RXD/GP3[1]</code> means that the pin can be used as:
| J2.95||TIM7_IO/GP0_28||CPU.MCA[5]_AXR[1]/MCA[4]_AXR[3]/TIM7_IO/GP0[28]||L6||||I/O||||
|-
| J2.97||EN_BCK2_LS||PMIC.GPIO7GPIO0||L4||||O||||3.3V I/O Power Rail Enable- J2 pin 97 is connected to PMIC GPIO0. This pin is a 5V push-pull signal connected to a voltage divider circuit via 5K6 /10K resistor, thus providing the 3V3 logical voltage output (please see [[Pinout_(Naon)#EN_BCK2_LS_signal]]).
|-
| J2.99||SPI3_SCLKGP3_15||CPU.VOUT[1]_R_CR[5]/EMAC[1]_MTXD[4]/VIN[1]A_D[16]/PATA_D[8]/SPI[3]_SCLK/GP3[15]||AC26||||I/O||||
| J2.94||JTAG_RTCK||CPU.RTCK||AD4||||I||||
|-
| J2.96||JTAG_TDO||CPU.TDO||AD4AC5||||O||||
|-
| J2.98||JTAG_TCK||CPU.TCK||AC5W7||||I||||
|-
| J2.100||JTAG_TRSTn||CPU.TRSTn||AA4||||I||||
==Additional notes==
(1) Some pins support multiple routing options. Selected option is populated at manufacturing stage and can not be changed at later time.
=== EMAC_RMREFCLK ===
EMAC_REFCLK signal is the reference clock for the internal PHY (SMSC LAN8710) connected to EMAC[0] configured in RMII mode. This signal is driven by the CPU and can be optionally routed to J1.91 through a mount option. For more flexibility on using both EMAC[0] and EMAC[1] interfaces, this signal has been routed to the J1 connector providing the following configuration options:
* generated internally (default configuration) and routed externally for driving an external RMII PHY on the second MAC (EMAC[1]) at 10/100 Mbit. In this case it is possible to avoid the cost of an external crystal or oscillator.
* generated by an external PHY mounted on the carrier board (connected to EMAC[1]) and routed internally to the internal PHY and CPU. In some cases this configuration could be preferred.
=== EN_BCK2_LS signal ===
J2 pin 97 is connected to PMIC GPIO0. This pin is a 5V push-pull signal connected to a voltage divider circuit via 5K6 /10K resistor, thus providing the 3V3 logical voltage output as depicted below:
[[File:Maya_EN_BCK2_LS.jpg]]