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* generated internally (default configuration) and routed externally for driving an external RMII PHY on the second MAC (EMAC[1]) at 10/100 Mbit. In this case it is possible to avoid the cost of an external crystal or oscillator.
* generated by an external PHY mounted on the carrier board (connected to EMAC[1]) and routed internally to the internal PHY and CPU. In some cases this configuration could be preferred.
=== EN_BCK2_LS signal ===
J2 pin 97 is connected to PMIC GPIO0. This pin is a 5V push-pull signal connected to a voltage divider circuit via 5K6 /10K resistor, thus providing the 3V3 logical voltage output as depicted below:
[[File:Maya_EN_BCK2_LS.jpg]]