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→204-PIN SODIMM pinout
| 44||SD0_CLK||CPU.SD0_CLK/GP0[1]||Y6||||I/O||3.3V||
|-
| 45||EN_BCK2_LS||PMIC.GPIO0; 3.3V I/O Power Rail Enable (active high)||L4||||O||3.3V||SO-DIMM pin 45 is connected to PMIC GPIO0. The pin is a 5V push-pull signal connected to a voltage divider circuit via 5K6 /10K resistor, thus providing the 3V3 logical voltage output(please see [[Pinout_(Maya)#EN_BCK2_LS_signal]]).
|-
| 46||DGND||Ground||||||||||
==Additional notes==
(1) Some pins support multiple routing options. Selected option is populated at manufacturing stage and can not be changed at later time.
=== EN_BCK2_LS signal ===
This pin is a 5V push-pull signal connected to a voltage divider circuit via 5K6 /10K resistor, thus providing the 3V3 logical voltage output as depicted below:
[[File:Maya_EN_BCK2_LS.jpg]]
