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→204-PIN SODIMM pinout
==Introduction==
This chapter contains the pinout description of 204-pin DDR3 SODIMM edge connector of Maya module.
[[File:Maya_04.jpg|300px|frameless|border]]
Each row in the pinout table contains the following information:
* Pin: reference to the connector pin
| General purpose timer. “x” represents the terminal number (0 to 7)
|}
==204-PIN SODIMM pinout==
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;"|'''Voltage'''
| align="center" style="background:#f0f0f0;"|'''Note'''
|-
| 1||DGND||Ground||||||||||
|-
| 12||3.3V||3.3V power supply||||||||||
|-
| 13||JTAG_TCK||CPU.TCK||AC5W7||||I||3.3V||
|-
| 14||DGND||Ground||||||||||
|-
| 15||JTAG_RTCK||CPU.RTCK||AD4||||IO||3.3V||
|-
| 16||VBAT||PMIC.VBACKUP||D7||||S||||
| 18||TV_OUT1||CPU.TV_OUT0||AH24||||O||||
|-
| 19||JTAG_TDO||CPU.TDO||AD4AC5||||O||3.3V||
|-
| 20||SD1_DAT0||CPU.SD1_DAT[0]||P1||||I/O||3.3V||
| 44||SD0_CLK||CPU.SD0_CLK/GP0[1]||Y6||||I/O||3.3V||
|-
| 45||EN_BCK2_LS||PMIC.GPIO7GPIO0; 3.3V I/O Power Rail Enable (active high)||L4||||O||3.3V||10 kOhm pullSO-up DIMM pin 45 is connected to 3PMIC GPIO0.3VThe pin is a 5V push-pull signal connected to a voltage divider circuit via 5K6 /10K resistor, thus providing the 3V3 logical voltage output (please see [[Pinout_(Maya)#EN_BCK2_LS_signal]]).
|-
| 46||DGND||Ground||||||||||
==Additional notes==
(1) Some pins support multiple routing options. Selected option is populated at manufacturing stage and can not be changed at later time.
=== EN_BCK2_LS signal ===
This pin is a 5V push-pull signal connected to a voltage divider circuit via 5K6 /10K resistor, thus providing the 3V3 logical voltage output as depicted below:
[[File:Maya_EN_BCK2_LS.jpg]]
