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Following table lists pins available on SODIMM-204 edge connector of [[Diva SOM]].
{| class="wikitable" {{table}}| align="center" style="background:#f0f0f0;"|'''Pin #'''
| align="center" style="background:#f0f0f0;"|'''Pin name'''
| align="center" style="background:#f0f0f0;"|'''Internal connection(s)'''
| 1||DGND||||||||||||
|-
| 2||AM335X_GPMC_WPn||CPU.[GPMC_WPN/GMII2_RXERR/GPMC_CSN5/RMII2_RXERR/MMC2_SDCD/PR1_MII1_TXEN/UART4_TXD/GPIO0_31]||U17||||||||
|-
| 3||PMIC_VBACKUPAM335X_I2C0_SCL||PMICCPU.VBACKUP[I2C0_SCL/TIMER7/UART2_RTSN/ECAP1_IN_PWM1_OUT////GPIO3_6]||27C16||||||||
|-
| 4||AM335X_GPMC_CS0n||CPU.[GPMC_CSN0///////GPIO1_29]||V6||||||||
|-
| 5||PORSTnAM335X_I2C0_SDA||CPU.[I2C0_SDA/TIMER4/UART2_CTSN/ECAP2_IN_PWM2_OUT////GPIO3_5]||C17||||||||
|-
| 6||AM335X_GPMC_CS1n||CPU.[GPMC_CSN1/GPMC_CLK/MMC1_CLK/PR1_EDIO_DATA_IN6/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_12/PR1_PRU1_PRU_R31_12/GPIO1_30]||U9||||||||
|-
| 7||WARMRSTnWD_SET0||||||||||||
|-
| 8||AM335X_GPMC_CS2n||CPU.[GPMC_CSN2/GPMC_BE1N/MMC1_CMD/PR1_EDIO_DATA_IN7/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_13/PR1_PRU1_PRU_R31_13/GPIO1_31]||V9||||||||
|-
| 9||RTC_PWRONRSTnWD_SET1||CPU.RTC_PWRONRSTn||B5||||||||
|-
| 10||AM335X_GPMC_CS3n||CPU.[GPMC_CSN3///MMC2_CMD/PR1_MII0_CRS/PR1_MDIO_DATA/EMU4/GPIO2_0]||T13||||||||
|-
| 11||MRSTnWD_SET2||||||||||||
|-
| 12||DGND||||||||||||
|-
| 13||PMIC_nRESPWRONEEPROM_WP||||||||||||
|-
| 14||AM335X_GPMC_CLK||CPU.[GPMC_CLK/LCD_MEMORY_CLK/GPMC_WAIT1/MMC2_CLK/PR1_MII1_CRS/PR1_MDIO_MDCLK/MCASP0_FSR/GPIO2_1]||V12||||||||
|-
| 15||PMIC_PWRONEEPROM_A1||||||||||||
|-
| 16||AM335X_GPMC_WEn||CPU.[GPMC_WEN//TIMER6/////GPIO2_4]||U6||||||||
|-
| 17||PMIC_SLEEPEEPROM_A0||PMIC.SLEEP||37||||||||
|-
| 18||AM335X_GPMC_OEn_REn||CPU.[GPMC_OEN_REN//TIMER6/////GPIO2_4]||T7||||||||
|-
| 19||PMIC_INT1AM335X_EXT_WAKEUP||PMICCPU.INT1EXT_WAKEUP||45C5||||||||
|-
| 20||AM335X_GPMC_ADVn_ALE||CPU.[GPMC_ADVN_ALE//TIMER4/////GPIO2_2]||R7||||||||
|-
| 21||DGND||||||||||||
|-
| 22||AM335X_GPMC_BE0n_CLE||CPU.[GPMC_BE0N_CLE//TIMER5/////GPIO2_5]||T6||||||||
|-
| 23||PMIC_PWR_ENAM335X_RMII1_REFCLK||CPU.PMIC_PWR_EN, PMIC.PWRHOLD||CPU.C6, PMIC.1H18||||||||
|-
| 24||AM335X_GPMC_BE1n||CPU.[GPMC_BE1N/GMII2_COL/GPMC_CSN6/MMC2_DAT3/GPMC_DIR/PR1_MII1_RXLINK/MCASP0_ACLKR/GPIO1_28]||U18||||||||
|-
| 25||JTAG_TCKAM335X_UART0_TXD||CPU.TCK[UART0_TXD/SPI1_CS1/DCAN0_RX/I2C2_SCL/ECAP1_IN_PWM1_OUT/PR1_PRU1_PRU_R30_15/PR1_PRU1_PRU_R31_15/GPIO1_11]||E16||||||||
|-
| 26||AM335X_GPMC_WAIT||CPU.[GPMC_WAIT0/GMII2_CRS/GPMC_CSN4/RMII2_CRS_DV/MMC1_SDCD/PR1_MII1_COL/UART4_RXD/GPIO0_30]||T17||||||||
|-
| 27||JTAG_TRSTnAM335X_UART0_RXD||CPU.TRSTn[UART0_RXD/SPI1_CS0/DCAN0_TX/I2C2_SDA/ECAP2_IN_PWM2_OUT/PR1_PRU1_PRU_R30_14/PR1_PRU1_PRU_R31_14/GPIO1_10]||E15||||||||
|-
| 28||AM335X_GPMC_A0||CPU.[GPMC_A0/GMII2_TXEN/RGMII2_TCTL/RMII2_TXEN/GPMC_A16/PR1_MII_MT1_CLK/EHRPWM1_TRIPZONE_INPUT/GPIO1_16]||R13||||||||
|-
| 29||JTAG_TMSAM335X_UART0_RTSn||CPU.TMS[UART0_RTSN/UART4_TXD/DCAN1_RX/I2C1_SCL/SPI1_D1/SPI1_CS0/PR1_EDC_SYNC1_OUT/GPIO1_9]||E17||||||||
|-
| 30||AM335X_GPMC_A1||CPU.[GPMC_A1/GMII2_RXDV/RGMII2_RCTL/MMC2_DAT0/GPMC_A17/PR1_MII1_TXD3/EHRPWM0_SYNCO/GPIO1_17]||V14||||||||
|-
| 31||JTAG_TDIAM335X_UART0_CTSn||CPU.TDI[UART0_CTSN/UART4_RXD/DCAN1_TX/I2C1_SDA/SPI1_D0/TIMER7/PR1_EDC_SYNC0_OUT/GPIO1_8]||E18||||||||
|-
| 32||DGND||||||||||||
|-
| 33||JTAG_TDOAM335X_UART1_TXD||CPU.TDO[UART1_TXD/MMC2_SDWP/DCAN1_RX/I2C1_SCL//PR1_UART0_TXD/PR1_PRU0_PRU_R31_16/GPIO0_15]||D15||||||||
|-
| 34||AM335X_GPMC_A2||CPU.[GPMC_A2/GMII2_TXD3/RGMII2_TD3/MMC2_DAT1/GPMC_A18/PR1_MII1_TXD2/EHRPWM1A/GPIO1_18]||U14||||||||
|-
| 35||JTAG_EMU0AM335X_UART1_RXD||CPU.[EMU0UART1_RXD/MMC1_SDWP/DCAN1_TX/I2C1_SDA//PR1_UART0_RXD/PR1_PRU1_PRU_R31_16/GPIO3_7GPIO0_14]||D16||||||||
|-
| 36||AM335X_GPMC_A3||CPU.[GPMC_A3/GMII2_TXD2/RGMII2_TD2/MMC2_DAT2/GPMC_A19/PR1_MII1_TXD1/EHRPWM1B/GPIO1_19]||T14||||||||
|-
| 37||JTAG_EMU1AM335X_UART1_RTSn||CPU.[EMU1UART1_RTSN/TIMER5/DCAN0_RX/I2C2_SCL/SPI1_CS1/PR1_UART0_RTS_N/PR1_EDC_LATCH1_IN/GPIO3_8GPIO0_13]||D17||||||||
|-
| 38||AM335X_GPMC_A4||CPU.[GPMC_A4/GMII2_TXD1/RGMII2_TD1/RMII2_TXD1/GPMC_A20/PR1_MII1_TXD0/EQEP1A_IN/GPIO1_20]||R14||||||||
|-
| 39||AM335X_UART0_TXDAM335X_UART1_CTSn||CPU.[UART0_TXDUART1_CTSN/SPI1_CS1TIMER6/DCAN0_RXDCAN0_TX/I2C2_SCLI2C2_SDA/ECAP1_IN_PWM1_OUTSPI1_CS0/PR1_PRU1_PRU_R30_15PR1_UART0_CTS_N/PR1_PRU1_PRU_R31_15PR1_EDC_LATCH0_IN/GPIO1_11GPIO0_12]||D18||||||||
|-
| 40||AM335X_GPMC_A5||CPU.[GPMC_A5/GMII2_TXD0/RGMII2_TD0/RMII2_TXD0/GPMC_A21/PR1_MII1_RXD3/EQEP1B_IN/GPIO1_21]||V15||||||||
|-
| 41||DGND||||||||||||
|-
| 42||AM335X_GPMC_A6||CPU.[GPMC_A6/GMII2_TXCLK/RGMII2_TCLK/MMC2_DAT4/GPMC_A22/PR1_MII1_RXD2/EQEP1_INDEX/GPIO1_22]||U15||||||||
|-
| 43||AM335X_UART0_RXDAM335X_SPI0_SCLK||CPU.[UART0_RXDSPI0_SCLK/SPI1_CS0UART2_RXD/DCAN0_TXI2C2_SDA/I2C2_SDAEHRPWM0A/ECAP2_IN_PWM2_OUTPR1_UART0_CTS_N/PR1_PRU1_PRU_R30_14PR1_EDIO_SOF/PR1_PRU1_PRU_R31_14EMU2/GPIO1_10GPIO0_2]||A17||||||||
|-
| 44||AM335X_GPMC_A7||CPU.[GPMC_A7/GMII2_RXCLK/RGMII2_RCLK/MMC2_DAT5/GPMC_A23/PR1_MII1_RXD1/EQEP1_STROBE/GPIO1_23]||T15||||||||
|-
| 45||AM335X_UART0_RTSnAM335X_SPI0_D0||CPU.[UART0_RTSNSPI0_D0/UART4_TXDUART2_TXD/DCAN1_RXI2C2_SCL/I2C1_SCLEHRPWM0B/SPI1_D1PR1_UART0_RTS_N/SPI1_CS0PR1_EDIO_LATCH_IN/PR1_EDC_SYNC1_OUTEMU3/GPIO1_9GPIO0_3]||B17||||||||
|-
| 46||AM335X_GPMC_A8||CPU.[GPMC_A8/GMII2_RXD3/RGMII2_RD3/MMC2_DAT6/GPMC_A24/PR1_MII1_RXD0/MCASP0_ACLKX/GPIO1_24]||V16||||||||
|-
| 47||AM335X_UART0_CTSnAM335X_SPI0_D1||CPU.[UART0_CTSNSPI0_D1/UART4_RXDMMC1_SDWP/DCAN1_TXI2C1_SDA/I2C1_SDAEHRPWM0_TRIPZONE_INPUT/SPI1_D0PR1_UART0_RXD/TIMER7PR1_EDIO_DATA_IN0/PR1_EDC_SYNC0_OUTPR1_EDIO_DATA_OUT0/GPIO1_8GPIO0_4]||B16||||||||
|-
| 48||AM335X_GPMC_A9||CPU.[GPMC_A9/GMII2_RXD2/RGMII2_RD2/MMC2_DAT7/GPMC_A25/PR1_MII_MR1_CLK/MCASP0_FSX/GPIO1_25]||U16||||||||
|-
| 49||AM335X_UART1_TXDAM335X_SPI0_CS0||CPU.[UART1_TXDSPI0_CS0/MMC2_SDWP/DCAN1_RX/I2C1_SCL/EHRPWM0_SYNCI/PR1_UART0_TXD/PR1_PRU0_PRU_R31_16PR1_EDIO_DATA_IN1/PR1_EDIO_DATA_OUT1/GPIO0_15GPIO0_5]||A16||||||||
|-
| 50||AM335X_GPMC_A10||CPU.[GPMC_A10/GMII2_RXD1/RGMII2_RD1/RMII2_RXD1/GPMC_A26/PR1_MII1_RXDV/MCASP0_AXR0/GPIO1_26]||T16||||||||
|-
| 51||AM335X_UART1_RXDAM335X_SPI0_CS1||CPU.[UART1_RXDSPI0_CS1/MMC1_SDWPUART3_RXD/DCAN1_TXECAP1_IN_PWM1_OUT/I2C1_SDAMMC0_POW/XDMA_EVENT_INTR2/PR1_UART0_RXDMMC0_SDCD/PR1_PRU1_PRU_R31_16EMU4/GPIO0_14GPIO0_6]||C15||||||||
|-
| 52||DGND||||||||||||
|-
| 53||AM335X_UART1_RTSnUSB0_CE||CPU.[UART1_RTSN/TIMER5/DCAN0_RX/I2C2_SCL/SPI1_CS1/PR1_UART0_RTS_N/PR1_EDC_LATCH1_IN/GPIO0_13]USB0_CE||M15||||||||
|-
| 54||AM335X_GPMC_A11||CPU.[GPMC_A11/GMII2_RXD0/RGMII2_RD0/RMII2_RXD0/GPMC_A27/PR1_MII1_RXER/MCASP0_AXR1/GPIO1_27]||V17||||||||
|-
| 55||AM335X_UART1_CTSnUSB0_ID||CPU.[UART1_CTSN/TIMER6/DCAN0_TX/I2C2_SDA/SPI1_CS0/PR1_UART0_CTS_N/PR1_EDC_LATCH0_IN/GPIO0_12]USB0_ID||P16||||||||
|-
| 56||AM335X_GPMC_AD0||CPU.[GPMC_AD0/MMC1_DAT0//////GPIO1_0]||U7||||||||
|-
| 57||AM335X_I2C0_SCLUSB0_DP||CPU.[I2C0_SCL/TIMER7/UART2_RTSN/ECAP1_IN_PWM1_OUT////GPIO3_6]USB0_DP||N17||||||||
|-
| 58||AM335X_GPMC_AD1||CPU.[GPMC_AD1/MMC1_DAT1//////GPIO1_1]||V7||||||||
|-
| 59||AM335X_I2C0_SDAUSB0_DM||CPU.[I2C0_SDA/TIMER4/UART2_CTSN/ECAP2_IN_PWM2_OUT////GPIO3_5]USB0_DM||N18||||||||
|-
| 60||AM335X_GPMC_AD2||CPU.[GPMC_AD2/MMC1_DAT2//////GPIO1_2]||R8||||||||
|-
| 61||DGND||||||||||||
|-
| 62||AM335X_GPMC_AD3||CPU.[GPMC_AD3/MMC1_DAT3//////GPIO1_3]||T8||||||||
|-
| 63||AM335X_SPI0_SCLKUSB0_DRVVBUS||CPU.[SPI0_SCLK/UART2_RXD/I2C2_SDA/EHRPWM0A/PR1_UART0_CTS_N/PR1_EDIO_SOF/EMU2/GPIO0_2]USB0_DRVVBUS||F16||||||||
|-
| 64||AM335X_GPMC_AD4||CPU.[GPMC_AD4/MMC1_DAT4//////GPIO1_4]||U8||||||||
|-
| 65||AM335X_SPI0_D0VUSB_VBUS0||CPU.[SPI0_D0/UART2_TXD/I2C2_SCL/EHRPWM0B/PR1_UART0_RTS_N/PR1_EDIO_LATCH_IN/EMU3/GPIO0_3]USB0_VBUS||P15||||||||
|-
| 66||AM335X_GPMC_AD5||CPU.[GPMC_AD5/MMC1_DAT5//////GPIO1_5]||V8||||||||
|-
| 67||AM335X_SPI0_D1AM335x_EXTINTn||CPU.[SPI0_D1/MMC1_SDWP/I2C1_SDA/EHRPWM0_TRIPZONE_INPUT/PR1_UART0_RXD/PR1_EDIO_DATA_IN0/PR1_EDIO_DATA_OUT0/GPIO0_4]NMIn||B18||||||||
|-
| 68||AM335X_GPMC_AD6||CPU.[GPMC_AD6/MMC1_DAT6//////GPIO1_6]||R9||||||||
|-
| 69||AM335X_SPI0_CS0AM335X_XDMA_EVENT_INTR0||CPU.[SPI0_CS0XDMA_EVENT_INTR0/MMC2_SDWP/I2C1_SCLTIMER4/EHRPWM0_SYNCICLKOUT1/PR1_UART0_TXDSPI1_CS1/PR1_EDIO_DATA_IN1PR1_PRU1_PRU_R31_16/PR1_EDIO_DATA_OUT1EMU2/GPIO0_5GPIO0_19]||A15||||||||
|-
| 70||AM335X_GPMC_AD7||CPU.[GPMC_AD7/MMC1_DAT7//////GPIO1_7]||T9||||||||
|-
| 71||AM335X_SPI0_CS1AM335X_XDMA_EVENT_INTR1||CPU.[SPI0_CS1XDMA_EVENT_INTR1/UART3_RXD/ECAP1_IN_PWM1_OUTTCLKIN/MMC0_POWCLKOUT2/XDMA_EVENT_INTR2TIMER7/MMC0_SDCDPR1_PRU0_PRU_R31_16/EMU4EMU3/GPIO0_6GPIO0_20]||D14||||||||
|-
| 72||DGND||||||||||||
|-
| 73||USB0_CEUSB1_CE||CPU.USB0_CEUSB1_CE||P18||||||||
|-
| 74||AM335X_GPMC_AD8||CPU.[GPMC_AD8/LCD_DATA23/MMC1_DAT0/MMC2_DAT4/EHRPWM2A/PR1_MII_MT0_CLK//GPIO0_22]||U10||||||||
|-
| 75||USB0_IDUSB1_ID||CPU.USB0_IDUSB1_ID||P17||||||||
|-
| 76||AM335X_GPMC_AD9||CPU.[GPMC_AD9/LCD_DATA22/MMC1_DAT1/MMC2_DAT5/EHRPWM2B/PR1_MII0_COL//GPIO0_23]||T10||||||||
|-
| 77||USB0_DPUSB1_DP||CPU.USB0_DPUSB1_DP||R17||||||||
|-
| 78||AM335X_GPMC_AD10||CPU.[GPMC_AD10/LCD_DATA21/MMC1_DAT2/MMC2_DAT6/EHRPWM2_TRIPZONE_INPUT/PR1_MII0_TXEN//GPIO0_26]||T11||||||||
|-
| 79||USB0_DMUSB1_DM||CPU.USB0_DMUSB1_DM||R18||||||||
|-
| 80||AM335X_GPMC_AD11||CPU.[GPMC_AD11/LCD_DATA20/MMC1_DAT3/MMC2_DAT7/EHRPWM2_SYNCO/PR1_MII0_TXD3//GPIO0_27]||U12||||||||
|-
| 81||DGND||||||||||||
|-
| 82||AM335X_GPMC_AD12||CPU.[GPMC_AD12/LCD_DATA19/MMC1_DAT4/MMC2_DAT0/EQEP2A_IN/PR1_MII0_TXD2/PR1_PRU0_PRU_R30_14/GPIO1_12]||T12||||||||
|-
| 83||USB0_DRVVBUSUSB1_DRVVBUS||CPU.USB0_DRVVBUSUSB1_DRVVBUS||F15||||||||
|-
| 84||AM335X_GPMC_AD13||CPU.[GPMC_AD13/LCD_DATA18/MMC1_DAT5/MMC2_DAT1/EQEP2B_IN/PR1_MII0_TXD1/PR1_PRU0_PRU_R30_15/GPIO1_13]||R12||||||||
|-
| 85||VUSB_VBUS0VUSB_VBUS1||CPU.USB0_VBUSUSB1_VBUS||T18||||||||
|-
| 86||AM335X_GPMC_AD14||CPU.[GPMC_AD14/LCD_DATA17/MMC1_DAT6/MMC2_DAT2/EQEP2_INDEX/PR1_MII0_TXD0/PR1_PRU0_PRU_R31_14/GPIO1_14]||V13||||||||
|-
| 87||AM335x_EXTINTnAM335X_AIN0||CPU.NMInAIN0||B18B6||||||||
|-
| 88||AM335X_GPMC_AD15||CPU.[GPMC_AD15/LCD_DATA16/MMC1_DAT7/MMC2_DAT3/EQEP2_STROBE/PR1_ECAP0_ECAP_CAPIN_APWM_O/PR1_PRU0_PRU_R31_15/GPIO1_15]||U13||||||||
|-
| 89||AM335X_XDMA_EVENT_INTR0AM335X_AIN1||CPU.[XDMA_EVENT_INTR0//TIMER4/CLKOUT1/SPI1_CS1/PR1_PRU1_PRU_R31_16/EMU2/GPIO0_19]AIN1||A15C7||||||||
|-
| 90||AM335X_LCD_PCLK||CPU.[LCD_PCLK/GPMC_A10/PR1_MII0_CRS/PR1_EDIO_DATA_IN4/PR1_EDIO_DATA_OUT4/PR1_PRU1_PRU_R30_10/PR1_PRU1_PRU_R31_10/GPIO2_24]||V5||||||||
|-
| 91||AM335X_XDMA_EVENT_INTR1AM335X_AIN2||CPU.[XDMA_EVENT_INTR1//TCLKIN/CLKOUT2/TIMER7/PR1_PRU0_PRU_R31_16/EMU3/GPIO0_20]AIN2||D14B7||||||||
|-
| 92||DGND||||||||||||
|-
| 93||USB1_CEAGND_TSC||CPU.USB1_CE||||||||||
|-
| 94||AM335X_LCD_VSYNC||CPU.[LCD_VSYNC/GPMC_A8//PR1_EDIO_DATA_IN2/PR1_EDIO_DATA_OUT2/PR1_PRU1_PRU_R30_8/PR1_PRU1_PRU_R31_8/GPIO2_22]||U5||||||||
|-
| 95||USB1_IDAM335X_AIN3||CPU.USB1_IDAIN3||A7||||||||
|-
| 96||AM335X_LCD_HSYNC||CPU.[LCD_HSYNC/GPMC_A9//PR1_EDIO_DATA_IN3/PR1_EDIO_DATA_OUT3/PR1_PRU1_PRU_R30_9/PR1_PRU1_PRU_R31_9/GPIO2_23]||R5||||||||
|-
| 97||USB1_DPAM335X_AIN4||CPU.USB1_DPAIN4||C8||||||||
|-
| 98||AM335X_LCD_AC_BIAS_EN||CPU.[LCD_AC_BIAS_EN/GPMC_A11/PR1_MII1_CRS/PR1_EDIO_DATA_IN5/PR1_EDIO_DATA_OUT5/PR1_PRU1_PRU_R30_11/PR1_PRU1_PRU_R31_11/GPIO2_25]||R6||||||||
|-
| 99||USB1_DMAM335X_AIN5||CPU.USB1_DMAIN5||B8||||||||
|-
| 100||AM335X_LCD_DATA0||CPU.[LCD_DATA0/GPMC_A0/PR1_MII_MT0_CLK/EHRPWM2A//PR1_PRU1_PRU_R30_0/PR1_PRU1_PRU_R31_0/GPIO2_6]||R1||||||||
|-
| 101||DGNDAGND_TSC||||||||||||
|-
| 102||AM335X_LCD_DATA1||CPU.[LCD_DATA1/GPMC_A1/PR1_MII0_TXEN/EHRPWM2B//PR1_PRU1_PRU_R30_1/PR1_PRU1_PRU_R31_1/GPIO2_7]||R2||||||||
|-
| 103||USB1_DRVVBUSAM335X_AIN6||CPU.USB1_DRVVBUSAIN6||A8||||||||
|-
| 104||AM335X_LCD_DATA2||CPU.[LCD_DATA2/GPMC_A2/PR1_MII0_TXD3/EHRPWM2_TRIPZONE_INPUT//PR1_PRU1_PRU_R30_2/PR1_PRU1_PRU_R31_2/GPIO2_8]||R3||||||||
|-
| 105||VUSB_VBUS1AM335X_AIN7||CPU.USB1_VBUSAIN7||C9||||||||
|-
| 106||AM335X_LCD_DATA3||CPU.[LCD_DATA3/GPMC_A3/PR1_MII0_TXD2/EHRPWM2_SYNCI_O//PR1_PRU1_PRU_R30_3/PR1_PRU1_PRU_R31_3/GPIO2_9]||R4||||||||
|-
| 107||AM335X_ECAP0_IN_PWM0_OUTAGND_TSC||CPU.[ECAP0_IN_PWM0_OUT/UART3_TXD/SPI1_CS1/PR1_ECAP0_ECAP_CAPIN_APWM_O/SPI1_SCLK/MMC0_SDWP/XDMA_EVENT_INTR2/GPIO0_7]||||||||||
|-
| 108||AM335X_LCD_DATA4||CPU.[LCD_DATA4/GPMC_A4/PR1_MII0_TXD1/EQEP2A_IN//PR1_PRU1_PRU_R30_4/PR1_PRU1_PRU_R31_4/GPIO2_10]||T1||||||||
|-
| 109||AM335X_MMC_D3AM335X_ECAP0_IN_PWM0_OUT||CPU.[MMC0_DAT3ECAP0_IN_PWM0_OUT/GPMC_A20UART3_TXD/UART4_CTSNSPI1_CS1/TIMER5PR1_ECAP0_ECAP_CAPIN_APWM_O/UART1_DCDNSPI1_SCLK/PR1_PRU0_PRU_R30_8MMC0_SDWP/PR1_PRU0_PRU_R31_8XDMA_EVENT_INTR2/GPIO2_26GPIO0_7]||C18||||||||
|-
| 110||AM335X_LCD_DATA5||CPU.[LCD_DATA5/GPMC_A5/PR1_MII0_TXD0/EQEP2B_IN//PR1_PRU1_PRU_R30_5/PR1_PRU1_PRU_R31_5/GPIO2_11]||T2||||||||
|-
| 111||AM335X_MMC_D2AM335X_MMC_D3||CPU.[MMC0_DAT2MMC0_DAT3/GPMC_A21GPMC_A20/UART4_RTSNUART4_CTSN/TIMER6TIMER5/UART1_DSRNUART1_DCDN/PR1_PRU0_PRU_R30_9PR1_PRU0_PRU_R30_8/PR1_PRU0_PRU_R31_9PR1_PRU0_PRU_R31_8/GPIO2_27GPIO2_26]||F17||||||||
|-
| 112||DGND||||||||||||
|-
| 113||AM335X_MMC_D1AM335X_MMC_D2||CPU.[MMC0_DAT1MMC0_DAT2/GPMC_A22GPMC_A21/UART5_CTSNUART4_RTSN/UART3_RXDTIMER6/UART1_DTRNUART1_DSRN/PR1_PRU0_PRU_R30_10PR1_PRU0_PRU_R30_9/PR1_PRU0_PRU_R31_10PR1_PRU0_PRU_R31_9/GPIO2_28GPIO2_27]||F18||||||||
|-
| 114||AM335X_LCD_DATA6||CPU.[LCD_DATA6/GPMC_A6/PR1_EDIO_DATA_IN6/EQEP2_INDEX/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_6/PR1_PRU1_PRU_R31_6/GPIO2_12]||T3||||||||
|-
| 115||AM335X_MMC_D0AM335X_MMC_D1||CPU.[MMC0_DAT0MMC0_DAT1/GPMC_A23GPMC_A22/UART5_RTSNUART5_CTSN/UART3_TXDUART3_RXD/UART1_RINUART1_DTRN/PR1_PRU0_PRU_R30_11PR1_PRU0_PRU_R30_10/PR1_PRU0_PRU_R31_11PR1_PRU0_PRU_R31_10/GPIO2_29GPIO2_28]||G15||||||||
|-
| 116||AM335X_LCD_DATA7||CPU.[LCD_DATA7/GPMC_A7/PR1_EDIO_DATA_IN7/EQEP2_STROBE/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_7/PR1_PRU1_PRU_R31_7/GPIO2_13]||T4||||||||
|-
| 117||AM335X_MMC_CMDAM335X_MMC_D0||CPU.[MMC0_CMDMMC0_DAT0/GPMC_A25GPMC_A23/UART3_RTSNUART5_RTSN/UART2_TXDUART3_TXD/DCAN1_RXUART1_RIN/PR1_PRU0_PRU_R30_13PR1_PRU0_PRU_R30_11/PR1_PRU0_PRU_R31_13PR1_PRU0_PRU_R31_11/GPIO2_31GPIO2_29]||G16||||||||
|-
| 118||AM335X_LCD_DATA8||CPU.[LCD_DATA8/GPMC_A12/EHRPWM1_TRIPZONE_INPUT/MCASP0_ACLKX/UART5_TXD/PR1_MII0_RXD3/UART2_CTSN/GPIO2_14]||U1||||||||
|-
| 119||AM335X_MMC_CLKAM335X_MMC_CMD||CPU.[MMC0_CLKMMC0_CMD/GPMC_A24GPMC_A25/UART3_CTSNUART3_RTSN/UART2_RXDUART2_TXD/DCAN1_TXDCAN1_RX/PR1_PRU0_PRU_R30_12PR1_PRU0_PRU_R30_13/PR1_PRU0_PRU_R31_12PR1_PRU0_PRU_R31_13/GPIO2_30GPIO2_31]||G18||||||||
|-
| 120||AM335X_LCD_DATA9||CPU.[LCD_DATA9/GPMC_A13/EHRPWM1_SYNCO/MCASP0_FSX/UART5_RXD/PR1_MII0_RXD2/UART2_RTSN/GPIO2_15]||U2||||||||
|-
| 121||DGND||||||||||||
|-
| 122||AM335X_LCD_DATA10||CPU.[LCD_DATA10/GPMC_A14/EHRPWM1A/MCASP0_AXR0//PR1_MII0_RXD1/UART3_CTSN/GPIO2_16]||U3||||||||
|-
| 123||ETH_RX-AM335X_MMC_CLK||ETHPHYCPU.RXN[MMC0_CLK/GPMC_A24/UART3_CTSN/UART2_RXD/DCAN1_TX/PR1_PRU0_PRU_R30_12/PR1_PRU0_PRU_R31_12/GPIO2_30]||30G17||||||||
|-
| 124||AM335X_LCD_DATA11||CPU.[LCD_DATA11/GPMC_A15/EHRPWM1B/MCASP0_AHCLKR/MCASP0_AXR2/PR1_MII0_RXD0/UART3_RTSN/GPIO2_17]||U4||||||||
|-
| 125||ETH_RX+JTAG_EMU1||ETHPHYCPU.RXP[EMU1///////GPIO3_8]||31B14||||||||
|-
| 126||AM335X_LCD_DATA12||CPU.[LCD_DATA12/GPMC_A16/EQEP1A_IN/MCASP0_ACLKR/MCASP0_AXR2/PR1_MII0_RXLINK/UART4_CTSN/GPIO0_8]||V2||||||||
|-
| 127||ETH_TX-JTAG_EMU0||ETHPHYCPU.TXN[EMU0///////GPIO3_7]||28C14||||||||
|-
| 128||AM335X_LCD_DATA13||CPU.[LCD_DATA13/GPMC_A17/EQEP1B_IN/MCASP0_FSR/MCASP0_AXR3/PR1_MII0_RXER/UART4_RTSN/GPIO0_9]||V3||||||||
|-
| 129||ETH_TX+JTAG_TDO||ETHPHYCPU.TXPTDO||29A11||||||||
|-
| 130||AM335X_LCD_DATA14||CPU.[LCD_DATA14/GPMC_A18/EQEP1_INDEX/MCASP0_AXR1/UART5_RXD/PR1_MII_MR0_CLK/UART5_CTSN/GPIO0_10]||V4||||||||
|-
| 131||EMAC0_PHY_LED_SPEEDJTAG_TDI||ETHPHYCPU.LED2/nINTSELTDI||2B11||||||||10kOhm pull-down
|-
| 132||DGND||||||||||||
|-
| 133||EMAC0_PHY_LED_LINK/ACTJTAG_TMS||ETHPHYCPU.LED1/nREGOFFTMS||3C11||||||||
|-
| 134||AM335X_LCD_DATA15||CPU.[LCD_DATA15/GPMC_A19/EQEP1_STROBE/MCASP0_AHCLKX/MCASP0_AXR3/PR1_MII0_RXDV/UART5_RTSN/GPIO0_11]||T5||||||||
|-
| 135||ETH_CTTDJTAG_TRSTn||CPU.TRSTn||B10||||||||
|-
| 136||AM335X_MCASP0_FSR||CPU.[MCASP0_FSR/EQEP0B_IN/MCASP0_AXR3/MCASP1_FSX/EMU2/PR1_PRU0_PRU_R30_5/PR1_PRU0_PRU_R31_5/GPIO3_19]||C13||||||||
|-
| 137||ETH_CTRDJTAG_TCK||CPU.TCK||A12||||||||
|-
| 138||AM335X_MCASP0_AXR1||CPU.[MCASP0_AXR1/EQEP0_INDEX//MCASP1_AXR0/EMU3/PR1_PRU0_PRU_R30_6/PR1_PRU0_PRU_R31_6/GPIO3_20]||D13||||||||
|-
| 139||AM335X_GMII1_TXD3ETH_CTTD||CPU.[GMII1_TXD3/DCAN0_TX/RGMII1_TD3/UART4_RXD/MCASP1_FSX/MMC2_DAT1/MCASP0_FSR/GPIO0_16]||||||||||
|-
| 140||AM335X_MCASP0_FSX||CPU.[MCASP0_FSX/EHRPWM0B//SPI1_D0/MMC1_SDCD/PR1_PRU0_PRU_R30_1/PR1_PRU0_PRU_R31_1/GPIO3_15]||B13||||||||
|-
| 141||DGND||||||||||||
|-
| 142||AM335X_MCASP0_AXR0||CPU.[MCASP0_AXR0/EHRPWM0_TRIPZONE_INPUT//SPI1_D1/MMC2_SDCD/PR1_PRU0_PRU_R30_2/PR1_PRU0_PRU_R31_2/GPIO3_16]||D12||||||||
|-
| 143||AM335X_GMII1_TXD2ETH_CTRD||CPU.[GMII1_TXD2/DCAN0_RX/RGMII1_TD2/UART4_TXD/MCASP1_AXR0/MMC2_DAT2/MCASP0_AHCLKX/GPIO0_17]||||||||||
|-
| 144||AM335X_MCASP0_AHCLKR||CPU.[MCASP0_AHCLKR/EHRPWM0_SYNCI_O/MCASP0_AXR2/SPI1_CS0/ECAP2_IN_PWM2_OUT/PR1_PRU0_PRU_R30_3/PR1_PRU0_PRU_R31_3/GPIO3_17]||C12||||||||
|-
| 145||AM335X_GMII1_RXDVETH_TX-||CPUETHPHY.[GMII1_RXDV/LCD_MEMORY_CLK/RGMII1_RCTL/UART5_TXD/MCASP1_ACLKX/MMC2_DAT0/MCASP0_ACLKR/GPIO3_4]TXN||28||||||||
|-
| 146||AM335X_MCASP0_ACLKR||CPU.[MCASP0_ACLKR/EQEP0A_IN/MCASP0_AXR2/MCASP1_ACLKX/MMC0_SDWP/PR1_PRU0_PRU_R30_4/PR1_PRU0_PRU_R31_4/GPIO3_18]||B12||||||||
|-
| 147||AM335X_GMII1_MDIO_CLKETH_TX+||CPUETHPHY.[MDIO_CLK/TIMER5/UART5_TXD/UART3_RTSN/MMC0_SDWP/MMC1_CLK/MMC2_CLK/GPIO0_1]TXP||29||||||||
|-
| 148||AM335X_MCASP0_AHCLKX||CPU.[MCASP0_AHCLKX/EQEP0_STROBE/MCASP0_AXR3/MCASP1_AXR1/EMU4/PR1_PRU0_PRU_R30_7/PR1_PRU0_PRU_R31_7/GPIO3_21]||A14||||||||
|-
| 149||AM335X_GMII1_MDIO_DATAETH_RX-||CPUETHPHY.[MDIO_DATA/TIMER6/UART5_RXD/UART3_CTSN/MMC0_SDCD/MMC1_CMD/MMC2_CMD/GPIO0_0]RXN||30||||||||
|-
| 150||AM335X_MCASP0_ACLKX||CPU.[MCASP0_ACLKX/EHRPWM0A//SPI1_SCLK/MMC0_SDCD/PR1_PRU0_PRU_R30_0/PR1_PRU0_PRU_R31_0/GPIO3_14]||A13||||||||
|-
| 151||AM335X_GMII1_COLETH_RX+||CPUETHPHY.[GMII1_COL/RMII2_REFCLK/SPI1_SCLK/UART5_RXD/MCASP1_AXR2/MMC2_DAT3/MCASP0_AXR2/GPIO3_0]RXP||31||||||||
|-
| 152||DGND||||||||||||
|-
| 153||AM335X_GMII1_RXD3EMAC0_PHY_LED_SPEED||CPUETHPHY.[GMII1_RXD3LED2/UART3_RXD/RGMII1_RD3/MMC0_DAT5/MMC1_DAT2/UART1_DTRN/MCASP0_AXR0/GPIO2_18]nINTSEL||2||||||||10kOhm pull-down
|-
| 154||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 155||AM335X_GMII1_RXD2EMAC0_PHY_LED_LINK/ACT||CPUETHPHY.[GMII1_RXD2/UART3_TXD/RGMII1_RD2/MMC0_DAT4/MMC1_DAT3/UART1_RIN/MCASP0_AXR1LED1/GPIO2_19]nREGOFF||3||||||||
|-
| 156||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 157||AM335X_GMII1_RXCLKAM335X_GMII1_TXD3||CPU.[GMII1_RXCLKGMII1_TXD3/UART2_TXDDCAN0_TX/RGMII1_RCLKRGMII1_TD3/MMC0_DAT6UART4_RXD/MMC1_DAT1MCASP1_FSX/UART1_DSRNMMC2_DAT1/MCASP0_FSXMCASP0_FSR/GPIO3_10GPIO0_16]||J18||||||||
|-
| 158||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 159||AM335X_GMII1_TXCLKAM335X_GMII1_TXD2||CPU.[GMII1_TXCLKGMII1_TXD2/UART2_RXDDCAN0_RX/RGMII1_TCLKRGMII1_TD2/MMC0_DAT7UART4_TXD/MMC1_DAT0MCASP1_AXR0/UART1_DCDNMMC2_DAT2/MCASP0_ACLKXMCASP0_AHCLKX/GPIO3_9GPIO0_17]||K15||||||||
|-
| 160||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
| 162||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 163||PMIC_CLK32OUTAM335X_GMII1_RXDV||PMICCPU.CLK32KOUT[GMII1_RXDV/LCD_MEMORY_CLK/RGMII1_RCTL/UART5_TXD/MCASP1_ACLKX/MMC2_DAT0/MCASP0_ACLKR/GPIO3_4]||PMIC.38J17||||||||
|-
| 164||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 165||RFUAM335X_GMII1_MDIO_CLK||CPU.[MDIO_CLK/TIMER5/UART5_TXD/UART3_RTSN/MMC0_SDWP/MMC1_CLK/MMC2_CLK/GPIO0_1]||M18||||||||This pin is reserved for future use and must not be connected.
|-
| 166||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 167||RFUAM335X_GMII1_MDIO_DATA||CPU.[MDIO_DATA/TIMER6/UART5_RXD/UART3_CTSN/MMC0_SDCD/MMC1_CMD/MMC2_CMD/GPIO0_0]||M17||||||||This pin is reserved for future use and must not be connected.
|-
| 168||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 169||RFUAM335X_GMII1_COL||CPU.[GMII1_COL/RMII2_REFCLK/SPI1_SCLK/UART5_RXD/MCASP1_AXR2/MMC2_DAT3/MCASP0_AXR2/GPIO3_0]||H16||||||||This pin is reserved for future use and must not be connected.
|-
| 170||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 171||RFUAM335X_GMII1_RXD3||CPU.[GMII1_RXD3/UART3_RXD/RGMII1_RD3/MMC0_DAT5/MMC1_DAT2/UART1_DTRN/MCASP0_AXR0/GPIO2_18]||L17||||||||This pin is reserved for future use and must not be connected.
|-
| 172||DGND||||||||||||
|-
| 173||AM335X_EXT_WAKEUPAM335X_GMII1_RXD2||CPU.EXT_WAKEUP[GMII1_RXD2/UART3_TXD/RGMII1_RD2/MMC0_DAT4/MMC1_DAT3/UART1_RIN/MCASP0_AXR1/GPIO2_19]||L16||||||||
|-
| 174||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 175||EEPROM_A0AM335X_GMII1_RXCLK||CPU.[GMII1_RXCLK/UART2_TXD/RGMII1_RCLK/MMC0_DAT6/MMC1_DAT1/UART1_DSRN/MCASP0_FSX/GPIO3_10]||L18||||||||
|-
| 176||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 177||EEPROM_A1AM335X_GMII1_TXCLK||CPU.[GMII1_TXCLK/UART2_RXD/RGMII1_TCLK/MMC0_DAT7/MMC1_DAT0/UART1_DCDN/MCASP0_ACLKX/GPIO3_9]||K18||||||||
|-
| 178||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 179||EEPROM_WPPMIC_CLK32OUT||PMIC.CLK32KOUT||PMIC.38||||||||
|-
| 180||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
| 182||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 183||AM335X_AIN7PMIC_PWR_EN||CPU.AIN7PMIC_PWR_EN, PMIC.PWRHOLD||CPU.C6, PMIC.1||||||||
|-
| 184||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 185||AM335X_AIN6PMIC_INT1||CPUPMIC.AIN6INT1||45||||||||
|-
| 186||VIN||||||||||||
|-
| 187||AM335X_AIN5PMIC_SLEEP||CPUPMIC.AIN5SLEEP||37||||||||
|-
| 188||VIN||||||||||||
|-
| 189||AM335X_AIN4PMIC_PWRON||CPU.AIN4||||||||||
|-
| 190||VIN||||||||||||
|-
| 191||RFUPMIC_nRESPWRON||||||||||||This pin is reserved for future use and must not be connected.
|-
| 192||DGND||||||||||||
|-
| 193||AM335X_AIN3MRSTn||CPU.AIN3||||||||||
|-
| 194||VIN||||||||||||
|-
| 195||AM335X_AIN2RTC_PWRONRSTn||CPU.AIN2RTC_PWRONRSTn||B5||||||||
|-
| 196||VIN||||||||||||
|-
| 197||AM335X_AIN1WARMRSTn||CPU.AIN1||||||||||
|-
| 198||VIN||||||||||||
|-
| 199||AM335X_AIN0PORSTn||CPU.AIN0||||||||||
|-
| 200||VIN||||||||||||
| 202||VIN||||||||||||
|-
| 203||RFUPMIC_VBACKUP||PMIC.VBACKUP||27||||||||This pin is reserved for future use and must not be connected.
|-
| 204||VIN||||||||||||
|-
|
|}
