3,260
edits
Changes
m
→J2 odd pins (1 to 139)
| J2.25||GPMC_A4/SD2_DAT0||CPU.SD2_DAT[0]/GPMC_A[4]/GP1[14]||L26||||I/O||||
|-
| J2.27||GPMC_A6/CAM_D2DGND||CPU.VOUT[1]_G_Y_YC[0]/CAM_D[2]/PATA_DA[2]/GPMC_A[6]/UART4_TXD/GP0[23]DGND||AC18-||||I/OG||||
|-
| J2.29||GPMC_A8/CAM_D0PCIE_TXP0||CPU.VOUT[1]_R_CR[0]/CAM_D[0]/PATA_DA[0]/GPMC_A[8]/UART4_RTSn/GP0[25]PCIE_TXP0||AA22AD2||||I/O||1.8V||
|-
| J2.31||GPMC_A10/CAM_VSPCIE_TXN0||CPU.VOUT[1]_B_CB_C[0]/CAM_VS/PATA_IORDY/GPMC_A[10]/UART2_TXD/GP0[27]PCIE_TXN0||AD23AD1||||I/O||1.8V||
|-
| J2.33||VOUT0_FLD/CAM_PCLK/GPMC_A12/GP2_02DGND||CPU.VOUT[0]_FLD/CAM_PCLK/GPMC_A[12]/UART2_RTSn/GP2[02]DGND||AF18-||||I/OG||||
|-
| J2.35||3.3V||+3V3||-||||S||||
| J2.39||GPMC_A14/I2C2_SDA||CPU.VOUT[1]_R_CR[3]/GPMC_A[14]/VIN[1]A_D[22]/HDMI_SDA/SPI[2]_SCLK/I2C[2]_SDA/GP3[21]||AG28||||I/O||||
|-
| J2.41||GPMC_A163.3V||CPU.GPMC_A[16]/GP2[5]+3V3||AD27-||||I/OS||||
|-
| J2.43||GPMC_A183.3V||CPU.GPMC_A[18]/TIM2_IO/GP1[13]+3V3||AE28-||||I/OS||||
|-
| J2.45||GPMC_A20||CPU.GPMC_A[20]/SPI[2]_SCS[1]n/GP1[15]||AD28||||I/O||||
| J2.95||TIM7_IO/GP0_28||CPU.MCA[5]_AXR[1]/MCA[4]_AXR[3]/TIM7_IO/GP0[28]||L6||||I/O||||
|-
| J2.97||EN_BCK2_LS||PMIC.GPIO0||L4L5||||O||||3.3V I/O Power Rail Enable - J2 pin 97 is connected to PMIC GPIO0. This pin is a 5V push-pull signal connected to a voltage divider circuit via 5K6 /10K resistor, thus providing the 3V3 logical voltage output (please see [[Pinout_(NaonDido)#EN_BCK2_LS_signal]]).
|-
| J2.99||SPI3_SCLKGP3_15||CPU.VOUT[1]_R_CR[5]/EMAC[1]_MTXD[4]/VIN[1]A_D[16]/PATA_D[8]/SPI[3]_SCLK/GP3[15]||AC26||||I/O||||
| J2.24||GPMC_A3/SD2_DAT1||CPU.SD2_DAT[1]_SDIRQn/GPMC_A[3]/GP1[13]||M24||||I/O||||
|-
| J2.26||GPMC_A5/CAM_D3DGND||CPU.VOUT[1]_G_Y_YC[1]/CAM_D[3]/GPMC_A[5]/UART4_RXD/GP0[22]DGND||AD18-||||I/OG||||
|-
| J2.28||GPMC_A7/CAM_D1PCIE_RXP0||CPU.VOUT[1]_R_CR[1]/CAM_D[1]/GPMC_A[7]/UART4_CTSn/GP0[24]PCIE_RXP0||AC19AC2||||I/O||1.8V||
|-
| J2.30||GPMC_A9/CAM_HSPCIE_RXN0||CPU.VOUT[1]_B_CB_C[1]/CAM_HS/GPMC_A[9]/UART2_RXD/GP0[26]PCIE_RXN0||AE23AC1||||I/O||1.8V||
|-
| J2.32||GPMC_A11/CAM_FLD/CAM_WEnDGND||CPU.VOUT[1]_FLD/CAM_FLD/CAM_WEn/GPMC_A[11]/UART2_CTSn/GP0[28]DGND||AB23-||||I/OG||||
|-
| J2.34||GPMC_A13/I2C2_SCL||CPU.VOUT[1]_G_Y_YC[2]/GPMC_A[13]/VIN[1]A_D[21]/HDMI_SCL/SPI[2]_SCS[2]n/I2C[2]_SCL/GP3[20]||AF27||||I/O||||
|-
| J2.36||GPMC_A15SERDES_CLKP||CPU.VOUT[1]_R_CR[2]/GPMC_A[15]/VIN[1]A_D[23]/HDMI_HPDET/SPI[2]_D[1]/GP3[22]SERDES_CLKP||AE27AF1||||I/O||-||
|-
| J2.38||GPMC_A17SERDES_CLKN||CPU.GPMC_A[17]/GP2[6]SERDES_CLKN||V23AF2||||I/O||-||
|-
| J2.40||GPMC_A19DGND||CPU.GPMC_A[19]/TIM3_IO/GP1[14]DGND||AC27-||||I/OG||||
|-
| J2.42||GPMC_A21||CPU.GPMC_A[21]/SPI[2]_D[0]/GP1[16]||AC28||||I/O||||
