Bureaucrats, dave_user, Administrators
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* Pin: reference to the connector pin
* Pin Name: pin (signal) name on the Bora connectorsBORA Lite connector* Internal connections: connections to the Bora BORA Lite components
** CPU.<x> : pin connected to CPU (processing system) pad named <x>
** FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>
|J1.39||PS_MIO41_501||CPU.PS_MIO41_501||C17||||||||
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|J1.41||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora Lite SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(BoraBoraLite)]].
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|J1.43||IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||V5|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.45||IO_L22P_T3_13||FPGA.IO_L22P_T3_13||V6|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.47||IO_L22N_T3_13||FPGA.IO_L22N_T3_13||W6|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.49||IO_L11P_T1_SRCC_13||FPGA.IO_L11P_T1_SRCC_13||U7|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.51||IO_L11N_T1_SRCC_13||FPGA.IO_L11N_T1_SRCC_13||V7|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.53||IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y6|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.55||IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y7|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.57||DGND||DGND||n.a.||||||||
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|J1.59||IO_L15N_T2_DQS_13||FPGA.IO_L15N_T2_DQS_13||W8|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.61||IO_L15P_T2_DQS_13||FPGA.IO_L15P_T2_DQS_13||V8|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.63||IO_L16P_T2_13||FPGA.IO_L16P_T2_13||W10|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.65||IO_L16N_T2_13||FPGA.IO_L16N_T2_13||W9|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.67||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora Lite SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
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|J1.69||IO_L14N_T2_SRCC_13||FPGA.IO_L14N_T2_SRCC_13||Y8|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.71||IO_L14P_T2_SRCC_13||FPGA.IO_L14P_T2_SRCC_13||Y9|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.73||DGND||DGND||n.a.||||||||
|-|J1.75||ETH0_PHY_RST||LAN.RESET_N||41||||||||Internally connected to PS_MIO51_501
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|J1.77||VDDIO_BANK34||FPGA.VCCO_BANK34||N19<br>R15<br>T18<br>V14<br>W17<br>Y20||||||||
|J1.79||IO_0_34||FPGA.IO_0_34||R19||||||||
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|J1.81||IO_25_34||FPGA.IO_25_34||T19||||||||Optionally connected to ETH PHY 25MHz OSC ENABLE<br>Optionally connected to USB 26MHz OSC ENABLE
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|J1.83||IO_L8N_T1_34||FPGA.IO_L8N_T1_34||Y14||||||||
|J1.2||DGND||DGND||n.a.||||||||
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|J2J1.4||3.3VIN||+3.3 V||n.a.||||||||
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|J2J1.6||3.3VIN||+3.3 V||n.a.||||||||
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|J2J1.8||3.3VIN||+3.3 V||n.a.||||||||
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|J2J1.10||3.3VIN||+3.3 V||n.a.||||||||
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|J1.12||DGND||DGND||n.a.||||||||
|J1.20||MRSTN||MTR.MR||6||||||||Optionally internally connected to PORSTn (CPU.PS_POR_B_500)
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|J2J1.22||VBAT_BKP||RTC.VBAT||6||||||||
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|J1.24||PS_MIO49_501||CPU.PS_MIO49_501||C12||||||||
|J1.56||DGND||DGND||n.a.||||||||
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|J3J1.58||IO_L17N_T2_13||FPGA.IO_L17N_T2_13||U8|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J3J1.60||IO_L17P_T2_13||FPGA.IO_L17P_T2_13||U9|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.62||IO_L12P_T1_MRCC_13||FPGA.IO_L12P_T1_MRCC_13||T9|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.64||IO_L12N_T1_MRCC_13||FPGA.IO_L12N_T1_MRCC_13||U10|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.66||IO_L19P_T3_13||FPGA.IO_L19P_T3_13||T5|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.68||IO_L19N_T3_VREF_13||FPGA.IO_L19N_T3_VREF_13||U5|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.70||IO_L18P_T2_13||FPGA.IO_L18P_T2_13||W11|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.72||IO_L18N_T2_13||FPGA.IO_L18N_T2_13||Y11|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.74||IO_L21N_T3_DQS_13||FPGA.IO_L21N_T3_DQS_13||V10|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.76||IO_L21P_T3_DQS_13||FPGA.IO_L21P_T3_DQS_13||V11|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.78||IO_L20P_T3_13||FPGA.IO_L20P_T3_13||Y12|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.80||IO_L20N_T3_13||FPGA.IO_L20N_T3_13||Y13|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.82||DGND||DGND||n.a.||||||||
