Bureaucrats, dave_user, Administrators
8,146
edits
Changes
→J1 odd pins (1 to 203)
|J1.79||IO_0_34||FPGA.IO_0_34||R19||||||||
|-
|J1.81||IO_25_34||FPGA.IO_25_34||T19||||||||Optionally connected to ETH 25MHz OSC ENABLE<br>Optionally connected to USB 26MHz OSC ENABLE
|-
|J1.83||IO_L8N_T1_34||FPGA.IO_L8N_T1_34||Y14||||||||
