Bureaucrats, dave_user, Administrators
8,154
edits
Changes
→J1 odd pins (1 to 203)
|J1.39||PS_MIO41_501||CPU.PS_MIO41_501||C17||||||||
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|J1.41||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(BoraBoraLite)]].
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|J1.43||IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||V5|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
