__FORCETOC__ ==IntroductionConnectors and Pinout Table== === Connectors description ===In the following table are described all available connectors integrated on [[BORA Lite SOM]]:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM DDR3 edge connector 204 pin||TE Connectivity 2-2013289-1|}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA Lite pinout specifications. See the images below for reference: [[File:BORA_Lite-top-pin1-203.png|500px|thumb|BORA Lite TOP view|none]][[File:BORA_Lite-bottom-pin2-204.png|500px|thumb|BORA Lite BOTTOM view|none]] ===Pinout table naming conventions ===<section begin="Body" />

* {| class="wikitable" style="width:50%;"|-|'''Pin: reference '''| Reference to the connector pin* |-|'''Pin Name: pin ''' | Pin (signal) name on the BORA Lite connectorAxelLite connectors|-* |'''Internal <br>connections: connections ''' | Connections to the BORA Lite components** CPU.<x> : pin connected to CPU (processing system) pad named <x>** FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>** CAN.<x> : pin connected to the CAN transceiver** LAN.<x> : pin connected to the LAN PHY** USB.<x> : pin connected to the USB transceiver** NAND.<x>: pin connected to the flash NAND** NOR.<x>: pin connected to the flash NOR** SV.<x>: pin connected to voltage supervisor** MTR: pin connected to voltage monitors* |-|'''Ball/pin #: ''' | Component ball/pin number connected to signal* Supply Group: Power Supply Group|-|'''Voltage''' || I/O voltage levels |-* |'''Type''' | Pin type: pin type** I = Input** O = Output** D = Differential** Z = High impedance** S = Power supply voltage** G = Ground** A = Analog signal* Voltage: I/O voltage levels|-|'''Notes'''|Remarks on special pin characteristics|-|}

==J1 odd SODIMM ODD pins (1 to 203)declaration==

==J1 even SODIMM EVEN pins (2 to 204)declaration==

|J1.14||BOARD_PGOOD||PSUSWITCHFPGABANK13.ON<br>PSUSWITCHFPGABANK500/34.ON<br>PSUSWITCHFPGABANK35.ON<br>PSUSWITCHFPGABANK501.ON<br>DDRVREFREGULATOR.PGOOD||3<br>3<br>3<br>3<br>9||||||||Open-drain with internal pull-up (10K) to 3.3VINFor further details, please refer to [[Power (Bora/BoraLite)|Power Supply]]

|J1.16||CB_PWR_GOOD ||1V0REGULATOR.ENABLE ||n.a.||||||||For further details, please refer to [[Power (Bora/BoraLite)|Power Supply]]

|J1.18||SYS_RSTN||CPU.PS_SRST_B_501<br>MTR.~RST||B10<br>5||||||||For further details, please refer to [[Reset scheme (Bora/BoraLite)#Reset signals|Reset signals]]