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→SODIMM EVEN pins declaration
[[File:BORA_Lite-bottom-pin2-204.png|500px|thumb|BORA Lite BOTTOM view|none]]
===Pinout table naming conventions ===<section begin="Body" />
This chapter contains the pinout description of the BORA Lite SOM, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM BORA Lite connector.
Each row in the pinout tables contains the following information:
{| class="wikitable" style="width:50%;"
|}
==J1 even SODIMM EVEN pins (2 to 204)declaration==
{| class="wikitable" {| {{table}}
|J1.12||DGND||DGND||n.a.||||||||
|-
|J1.14||BOARD_PGOOD||PSUSWITCHFPGABANK13.ON<br>PSUSWITCHFPGABANK500/34.ON<br>PSUSWITCHFPGABANK35.ON<br>PSUSWITCHFPGABANK501.ON<br>DDRVREFREGULATOR.PGOOD||3<br>3<br>3<br>3<br>9||||||||Open-drain with internal pull-up (10K) to 3.3VINFor further details, please refer to [[Power (Bora/BoraLite)|Power Supply]]
|-
|J1.16||CB_PWR_GOOD ||1V0REGULATOR.ENABLE ||n.a.||||||||For further details, please refer to [[Power (Bora/BoraLite)|Power Supply]]
|-
|J1.18||SYS_RSTN||CPU.PS_SRST_B_501<br>MTR.~RST||B10<br>5||||||||For further details, please refer to [[Reset scheme (Bora/BoraLite)#Reset signals|Reset signals]]
|-
|J1.20||MRSTN||MTR.MR||6||||||||Optionally internally connected to PORSTn (CPU.PS_POR_B_500)
For further details, please refer to [[Reset scheme (Bora/BoraLite)#Reset signals|Reset signals]]
|-
|J1.22||VBAT_BKP||RTC.VBAT||6||||||||
|}
<section end="Body" />