Changes

Jump to: navigation, search

Pinout (BoraLite)

861 bytes added, 10:53, 7 September 2021
Pinout table naming conventions
{{InfoBoxBottom}}
__FORCETOC__ ==IntroductionConnectors and Pinout Table== === Connectors description ===In the following table are described all available connectors integrated on [[BORA Lite SOM]]:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM DDR3 edge connector 204 pin||TE Connectivity 2-2013289-1|}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA Lite pinout specifications. See the images below for reference: [[File:BORA_Lite-top-pin1-203.png|500px|thumb|BORA Lite TOP view|none]][[File:BORA_Lite-bottom-pin2-204.png|500px|thumb|BORA Lite BOTTOM view|none]] ===Pinout table naming conventions ===<section begin=Body/>
This chapter contains the pinout description of the BORA Lite SOM, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM BORA Lite connector.
Each row in the pinout tables contains the following information:
* Pin: reference to the connector pin
* Pin Name: pin (signal) name on the BORA Lite connector
* Internal connections: connections to the BORA Lite components
** CPU.<x> : pin connected to CPU (processing system) pad named <x>
** FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>
** CAN.<x> : pin connected to the CAN transceiver
** LAN.<x> : pin connected to the LAN PHY
** USB.<x> : pin connected to the USB transceiver
** NAND.<x>: pin connected to the flash NAND
** NOR.<x>: pin connected to the flash NOR
** SV.<x>: pin connected to voltage supervisor
** MTR: pin connected to voltage monitors
* Ball/pin #: Component ball/pin number connected to signal
* Supply Group: Power Supply Group
* Type: pin type
** I = Input
** O = Output
** D = Differential
** Z = High impedance
** S = Power supply voltage
** G = Ground
** A = Analog signal
* Voltage: I/O voltage levels
{| class="wikitable" style=J1 odd pins "width:50%;"|-|'''Pin'''| Reference to the connector pin|-|'''Pin Name''' | Pin (1 signal) name on the AxelLite connectors|-|'''Internal<br>connections''' | Connections to 203the components* CPU.<x> : pin connected to CPU (processing system)pad named <x>* FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>* CAN.<x> : pin connected to the CAN transceiver* LAN.<x> : pin connected to the LAN PHY* USB.<x> : pin connected to the USB transceiver* NAND.<x>: pin connected to the flash NAND* NOR.<x>: pin connected to the flash NOR* SV.<x>: pin connected to voltage supervisor* MTR: pin connected to voltage monitors|-|'''Ball/pin #''' | Component ball/pin number connected to signal|-|'''Voltage''' || I/O voltage levels |-|'''Type''' | Pin type:* I = Input* O = Output* D = Differential* Z = High impedance* S = Power supply voltage* G = Ground* A = Analog signal|-|'''Notes'''|Remarks on special pin characteristics|-|} ==SODIMM ODD pins declaration==
{| class="wikitable" {| {{table}}
|}
==J1 even SODIMM EVEN pins (2 to 204)declaration==
{| class="wikitable" {| {{table}}
|-
|}
 
<section end=Body/>
8,154
edits

Navigation menu