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__FORCETOC__ ==IntroductionConnectors and Pinout Table== === Connectors description ===In the following table are described all available connectors integrated on [[BORA Lite SOM]]:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM DDR3 edge connector 204 pin||TE Connectivity 2-2013289-1|}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA Lite pinout specifications. See the images below for reference: [[File:BORA_Lite-top-pin1-203.png|500px|thumb|BORA Lite TOP view|none]][[File:BORA_Lite-bottom-pin2-204.png|500px|thumb|BORA Lite BOTTOM view|none]] ===Pinout table naming conventions ===<section begin=Body/>
This chapter contains the pinout description of the BORA Lite SOM, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM BORA Lite connector.
Each row in the pinout tables contains the following information:
{| class="wikitable" style=J1 odd pins "width:50%;"|-|'''Pin'''| Reference to the connector pin|-|'''Pin Name''' | Pin (1 signal) name on the AxelLite connectors|-|'''Internal<br>connections''' | Connections to 203the components* CPU.<x> : pin connected to CPU (processing system)pad named <x>* FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>* CAN.<x> : pin connected to the CAN transceiver* LAN.<x> : pin connected to the LAN PHY* USB.<x> : pin connected to the USB transceiver* NAND.<x>: pin connected to the flash NAND* NOR.<x>: pin connected to the flash NOR* SV.<x>: pin connected to voltage supervisor* MTR: pin connected to voltage monitors|-|'''Ball/pin #''' | Component ball/pin number connected to signal|-|'''Voltage''' || I/O voltage levels |-|'''Type''' | Pin type:* I = Input* O = Output* D = Differential* Z = High impedance* S = Power supply voltage* G = Ground* A = Analog signal|-|'''Notes'''|Remarks on special pin characteristics|-|} ==SODIMM ODD pins declaration==
{| class="wikitable" {| {{table}}
|J1.41||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora Lite SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(BoraLite)]].
|-
|J1.43||IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||V5|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.45||IO_L22P_T3_13||FPGA.IO_L22P_T3_13||V6|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.47||IO_L22N_T3_13||FPGA.IO_L22N_T3_13||W6|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.49||IO_L11P_T1_SRCC_13||FPGA.IO_L11P_T1_SRCC_13||U7|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.51||IO_L11N_T1_SRCC_13||FPGA.IO_L11N_T1_SRCC_13||V7|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.53||IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y6|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.55||IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y7|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.57||DGND||DGND||n.a.||||||||
|-
|J1.59||IO_L15N_T2_DQS_13||FPGA.IO_L15N_T2_DQS_13||W8|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.61||IO_L15P_T2_DQS_13||FPGA.IO_L15P_T2_DQS_13||V8|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.63||IO_L16P_T2_13||FPGA.IO_L16P_T2_13||W10|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.65||IO_L16N_T2_13||FPGA.IO_L16N_T2_13||W9|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.67||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora Lite SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|J1.69||IO_L14N_T2_SRCC_13||FPGA.IO_L14N_T2_SRCC_13||Y8|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.71||IO_L14P_T2_SRCC_13||FPGA.IO_L14P_T2_SRCC_13||Y9|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.73||DGND||DGND||n.a.||||||||
|J1.79||IO_0_34||FPGA.IO_0_34||R19||||||||
|-
|J1.81||IO_25_34||FPGA.IO_25_34||T19||||||||Optionally connected to ETH 25MHz OSC ENABLE<br>Optionally connected to USB 26MHz OSC ENABLE
|-
|J1.83||IO_L8N_T1_34||FPGA.IO_L8N_T1_34||Y14||||||||
|}
==J1 even SODIMM EVEN pins (2 to 204)declaration==
{| class="wikitable" {| {{table}}
|J1.56||DGND||DGND||n.a.||||||||
|-
|J1.58||IO_L17N_T2_13||FPGA.IO_L17N_T2_13||U8|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.60||IO_L17P_T2_13||FPGA.IO_L17P_T2_13||U9|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.62||IO_L12P_T1_MRCC_13||FPGA.IO_L12P_T1_MRCC_13||T9|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.64||IO_L12N_T1_MRCC_13||FPGA.IO_L12N_T1_MRCC_13||U10|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.66||IO_L19P_T3_13||FPGA.IO_L19P_T3_13||T5|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.68||IO_L19N_T3_VREF_13||FPGA.IO_L19N_T3_VREF_13||U5|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.70||IO_L18P_T2_13||FPGA.IO_L18P_T2_13||W11|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.72||IO_L18N_T2_13||FPGA.IO_L18N_T2_13||Y11|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.74||IO_L21N_T3_DQS_13||FPGA.IO_L21N_T3_DQS_13||V10|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.76||IO_L21P_T3_DQS_13||FPGA.IO_L21P_T3_DQS_13||V11|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.78||IO_L20P_T3_13||FPGA.IO_L20P_T3_13||Y12|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.80||IO_L20N_T3_13||FPGA.IO_L20N_T3_13||Y13|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.82||DGND||DGND||n.a.||||||||
|-
|}
<section end=Body/>
