Pinout (Bora)

Connectors and Pinout Table

This chapter contains the pinout description of the Bora module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Bora connectors.

Connectors description

In the following table are described the interface connectors on Bora SOM:

Connector name	Connector Type	Notes	Carrier board counterpart
J1, J2, J3	Hirose FX8C-140S-SV 3x140 pins 0.6mm pitch connectors		Hirose FX8C-140P-SV<x> where <x> stays for: empty = 5 mm board-to-board height 1 = 6 mm board-to-board height 2 = 7 mm board-to-board height 4 = 9 mm board-to-board height 6 = 11 mm board-to-board height

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA pinout specifications. See the images below for reference:

BORA BOTTOM view - J1, J2, J3 connectors (pins 1-139, 2-140)

Pinout table naming conventions

Each row in the pinout tables contains the following information:

Pin	Reference to the connector pin
Pin Name	Pin (signal) name on the AxelLite connectors
Internal connections	Connections to the components CPU.<x> : pin connected to CPU pad named <x> CAN.<x> : pin connected to the CAN transceiver (TI SN65HVD232) LAN.<x> : pin connected to the LAN PHY (Microchip KSZ9031) USB.<x>: pin connected to the USB PHY (Microchip USB3317) NOR.<x>: pin connected to the NOR flash NAND.<x>: pin connected to the NAND flash IO_L<x>: pin connected to PL (FPGA) MTR: pin connected to voltage monitors MON_<x>: pin for external voltage monitoring
Ball/pin #	Component ball/pin number connected to signal
Voltage	I/O voltage levels 1.8V 3.3V U.D. = User Defined
Type	Pin type: I = Input O = Output D = Differential Z = High impedance S = Power supply voltage G = Ground A = Analog signal A/G = Analog Ground
Notes	Remarks on special pin characteristics

SOM J1 ODD pins (1 to 139) declaration

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J1.1	DGND	DGND	-		G
J1.3	IO_L7P_T1_AD2P_35	FPGA.IO_L7P_T1_AD2P_35	M19	BANK35	I/O	U.D.
J1.5	IO_L10P_T1_AD11P_35	FPGA.IO_L10P_T1_AD11P_35	K19	BANK35	I/O	U.D.
J1.7	IO_L11P_T1_SRCC_35	FPGA.IO_L11P_T1_SRCC_35	L16	BANK35	I/O	U.D.
J1.9	IO_L8N_T1_AD10N_35	FPGA.IO_L8N_T1_AD10N_35	M18	BANK35	I/O	U.D.
J1.11	IO_L7N_T1_AD2N_35	FPGA.IO_L7N_T1_AD2N_35	M20	BANK35	I/O	U.D.
J1.13	DGND	DGND	-		G
J1.15	IO_L9P_T1_DQS_AD3P_35	FPGA.IO_L9P_T1_DQS_AD3P_35	L19	BANK35	I/O	U.D.
J1.17	IO_L9N_T1_DQS_AD3N_35	FPGA.IO_L9N_T1_DQS_AD3N_35	L20	BANK35	I/O	U.D.
J1.19	DGND	DGND	-		G
J1.21	IO_L20P_T3_AD6P_35	FPGA.IO_L20P_T3_AD6P_35	K14	BANK35	I/O	U.D.
J1.23	IO_L20N_T3_AD6N_35	FPGA.IO_L20N_T3_AD6N_35	J14	BANK35	I/O	U.D.
J1.25	IO_L22P_T3_AD7P_35	FPGA.IO_L22P_T3_AD7P_35	L14	BANK35	I/O	U.D.
J1.27	IO_L12N_T1_MRCC_35	FPGA.IO_L12N_T1_MRCC_35	K18	BANK35	I/O	U.D.
J1.29	DGND	DGND	-		G
J1.31	IO_L21P_T3_DQS_AD14P_35	FPGA.IO_L21P_T3_DQS_AD14P_35	N15	BANK35	I/O	U.D.
J1.33	IO_L21N_T3_DQS_AD14N_35	FPGA.IO_L21N_T3_DQS_AD14N_35	N16	BANK35	I/O	U.D.
J1.35	DGND	DGND	-		G
J1.37	IO_L17N_T2_AD5N_35	FPGA.IO_L17N_T2_AD5N_35	H20	BANK35	I/O	U.D.
J1.39	IO_L13N_T2_MRCC_35	FPGA.IO_L13N_T2_MRCC_35	H17	BANK35	I/O	U.D.
J1.41	IO_L19P_T3_35	FPGA.IO_L19P_T3_35	H15	BANK35	I/O	U.D.
J1.43	IO_L18P_T2_AD13P_35	FPGA.IO_L18P_T2_AD13P_35	G19	BANK35	I/O	U.D.
J1.45	IO_L16P_T2_35	FPGA.IO_L16P_T2_35	G17	BANK35	I/O
J1.47	IO_L15N_T2_DQS_AD12N_35	FPGA.IO_L15N_T2_DQS_AD12N_35	F20	BANK35	I/O	U.D.
J1.49	DGND	DGND	-		G
J1.51	IO_L2N_T0_AD8N_35	FPGA.IO_L2N_T0_AD8N_35	A20	BANK35	I/O	U.D.
J1.53	IO_L1N_T0_AD0N_35	FPGA.IO_L1N_T0_AD0N_35	B20	BANK35	I/O	U.D.
J1.55	IO_L5N_T0_AD9N_35	FPGA.IO_L5N_T0_AD9N_35	E19	BANK35	I/O	U.D.
J1.57	IO_L5P_T0_AD9P_35	FPGA.IO_L5P_T0_AD9P_35	E18	BANK35	I/O	U.D.
J1.59	DGND	DGND	-		G
J1.61	IO_L3P_T0_DQS_AD1P_35	FPGA.IO_L3P_T0_DQS_AD1P_35	E17	BANK35	I/O	U.D.
J1.63	IO_L3N_T0_DQS_AD1N_35	FPGA.IO_L3N_T0_DQS_AD1N_35	D18	BANK35	I/O	U.D.
J1.65	DGND	DGND	-		G
J1.67	VDDIO_BANK35	FPGA.VCCO_35	C19 F18 H14 J17 K20 M16	BANK35	S		User Defined: 1.8V to 3.3V (see Programmable logic (Bora) )
J1.69	XADC_AGND	FPGA.GNDADC_0	J10		A / G
J1.71	XADC_AGND	FPGA.GNDADC_0	J10		A / G
J1.73	PS_MIO45_501	CPU.PS_MIO45_501	B15	BANK501	I/O	1.8V
J1.75	PS_MIO44_501	CPU.PS_MIO44_501	F13	BANK501	I/O	1.8V
J1.77	PS_MIO43_501	CPU.PS_MIO43_501	A9	BANK501	I/O	1.8V
J1.79	PS_MIO42_501	CPU.PS_MIO42_501	E12	BANK501	I/O	1.8V
J1.81	PS_MIO41_501	CPU.PS_MIO41_501	C17	BANK501	I/O	1.8V
J1.83	DGND	DGND	-		G
J1.85	PS_MIO40_501	CPU.PS_MIO40_501	D14	BANK501	I/O	1.8V
J1.87	ETH_MDIO	CPU.PS_MIO53_501 LAN.MDIO	C11 37	BANK501	I/O	1.8V
J1.89	ETH_MDC	CPU.PS_MIO12_501 LAN.MDC	C10 36	BANK501	I/O	1.8V
J1.91	ETH_LED1	LAN.LED1 / PME_N1	17		I/O	1.8V	Internal 10K pull-up to DVDDH (i.e. PHYAD0 = 1) . Level translator needed if used @ 3V3
J1.93	ETH_LED2	LAN.LED2	15		I/O	1.8V	Internal 10K pull-up to DVDDH (i.e. PHYAD1 = 1) . Level translator needed if used @ 3V3
J1.95	DGND	DGND	-		G
J1.97	ETH_TXRX1_M	LAN.TXRXM_B	6		D	3.3V
J1.99	ETH_TXRX1_P	LAN.TXRXP_B	5		D	3.3V
J1.101	DGND	DGND	-		G
J1.103	ETH_TXRX0_M	LAN.TXRXM_A	3		D	3.3V
J1.105	ETH_TXRX0_P	LAN.TXRXP_A	2		D	3.3V
J1.107	D.N.C	-					Do Not Connect (reserved for internal use)
J1.109	N.C.	Not Connected	-
J1.111	USBOTG_CPEN	USB.CPEN	7		O	1.8V	External 5V suply enable. For further details, please refer to the Microchip USB3317 datasheet.
J1.113	OTG_VBUS	USB.OTG_VBUS	2		I/O	5V	USB VBUS comparator. For further details, please refer to the Microchip USB3317 datasheet.
J1.115	OTG_ID	USB.ID	1		I	5V	ID of the USB cable. For further details, please refer to the Microchip USB3317 datasheet.
J1.117	DGND	DGND	-		G
J1.119	SPI0_DQ3/MODE0/NAND_IO0	CPU.PS_MIO5_500	A6	BANK500	I/O	3.3V	Internally connected as NAND I/O (if populated) This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
J1.121	SPI0_DQ2/MODE2/NAND_IO2	CPU.PS_MIO4_500	B7	BANK500	I/O	3.3V	Internally connected as NAND I/O (if populated) This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
J1.123	SPI0_DQ1/MODE1/NAND_WE	CPU.PS_MIO3_500	D6	BANK500	I/O	3.3V	Internally connected as NAND I/O (if populated) This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
J1.125	SPI0_DQ0/MODE3/NAND_ALE	CPU.PS_MIO2_500	B8	BANK500	I/O	3.3V	Internally connected as NAND I/O (if populated) This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
J1.127	DGND	DGND	-		G
J1.129	SPI0_SCLK/MODE4/NAND_IO1	CPU.PS_MIO6_500	A5	BANK500	I/O	3.3V	Internally connected as NAND I/O (if populated) This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
J1.131	NAND_BUSY	CPU.PS_MIO14_500	C5	BANK500	I/O	3.3V	Internally connected as NAND I/O (if populated)
J1.133	PS_MIO15_500	CPU.PS_MIO15_500 WDT.WDI	C8 1	BANK500	I/O	3.3V	See also this page
J1.135	N.C.	Not Connected	-
J1.137	MEM_WPN	NAND.WP - NOR.WP/IO2	19 - C4		I/O		Internally connected to NAND and NOR WP
J1.139	DGND	DGND	-		G

SOM J1 EVEN pins (2 to 140) declaration

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J1.2	VDDIO_BANK35	FPGA.VCCO_35	C19 F18 H14 J17 K20 M16	BANK35	S		User Defined: 1.8V to 3.3V (see Programmable logic (Bora) )
J1.4	DGND	DGND	-		G
J1.6	IO_L10N_T1_AD11N_35	FPGA.IO_L10N_T1_AD11N_35	J19	BANK35	I/O	U.D.
J1.8	IO_L12P_T1_MRCC_35	FPGA.IO_L12P_T1_MRCC_35	K17	BANK35	I/O	U.D.
J1.10	IO_L11N_T1_SRCC_35	FPGA.IO_L11N_T1_SRCC_35	L17	BANK35	I/O	U.D.
J1.12	IO_L8P_T1_AD10P_35	FPGA.IO_L8P_T1_AD10P_35	M17	BANK35	I/O	U.D.
J1.14	DGND	DGND	-		G
J1.16	IO_L24N_T3_AD15N_35	FPGA.IO_L24N_T3_AD15N_35	J16	BANK35	I/O	U.D.
J1.18	IO_25_35	FPGA.IO_25_35	J15	BANK35	I/O	U.D.
J1.20	IO_L24P_T3_AD15P_35	FPGA.IO_L24P_T3_AD15P_35	K16	BANK35	I/O	U.D.
J1.22	IO_L23N_T3_35	FPGA.IO_L23N_T3_35	M15	BANK35	I/O	U.D.
J1.24	DGND	DGND	-		G
J1.26	IO_L22N_T3_AD7N_35	FPGA.IO_L22N_T3_AD7N_35	L15	BANK35	I/O	U.D.
J1.28	IO_L23P_T3_35	FPGA.IO_L23P_T3_35	M14	BANK35	I/O	U.D.
J1.30	DGND	DGND	-		G
J1.32	IO_L17P_T2_AD5P_35	FPGA.IO_L17P_T2_AD5P_35	J20	BANK35	I/O	U.D.
J1.34	IO_L14P_T2_AD4P_SRCC_35	FPGA.IO_L14P_T2_AD4P_SRCC_35	J18	BANK35	I/O	U.D.
J1.36	IO_L14N_T2_AD4N_SRCC_35	FPGA.IO_L14N_T2_AD4N_SRCC_35	H18	BANK35	I/O	U.D.
J1.38	DGND	DGND	-		G
J1.40	IO_L13P_T2_MRCC_35	FPGA.IO_L13P_T2_MRCC_35	H16	BANK35	I/O	U.D.
J1.42	IO_L18N_T2_AD13N_35	FPGA.IO_L18N_T2_AD13N_35	G20	BANK35	I/O	U.D.
J1.44	IO_L16N_T2_35	FPGA.IO_L16N_T2_35	G18	BANK35	I/O	U.D.
J1.46	IO_L15P_T2_DQS_AD12P_35	FPGA.IO_L15P_T2_DQS_AD12P_35	F19	BANK35	I/O	U.D.
J1.48	DGND	DGND	-		G
J1.50	IO_L1P_T0_AD0P_35	FPGA.IO_L1P_T0_AD0P_35	C20	BANK35	I/O	U.D.
J1.52	IO_L2P_T0_AD8P_35	FPGA.IO_L2P_T0_AD8P_35	B19	BANK35	I/O	U.D.
J1.54	IO_L4N_T0_35	FPGA.IO_L4N_T0_35	D20	BANK35	I/O	U.D.
J1.56	IO_L4P_T0_35	FPGA.IO_L4P_T0_35	D19	BANK35	I/O	U.D.
J1.58	IO_L6P_T0_35	FPGA.IO_L6P_T0_35	F16	BANK35	I/O	U.D.
J1.60	DGND	DGND	-		G
J1.62	IO_L6N_T0_VREF_35	FPGA.IO_L6N_T0_VREF_35	F17	BANK35	I/O	U.D.
J1.64	IO_L19N_T3_VREF_35	FPGA.IO_L19N_T3_VREF_35	G15	BANK35	I/O	U.D.
J1.66	VDDIO_BANK35	FPGA.VCCO_35	C19 F18 H14 J17 K20 M16	BANK35	S		User Defined: 1.8V to 3.3V (see Programmable logic (Bora) )
J1.68	VDDIO_BANK35	FPGA.VCCO_35	C19 F18 H14 J17 K20 M16	BANK35	S		User Defined: 1.8V to 3.3V (see Programmable logic (Bora) )
J1.70	XADC_AGND	FPGA.GNDADC_0	J10		A/G
J1.72	XADC_AGND	FPGA.GNDADC_0	J10		A/G
J1.74	IO_0_35	FPGA.IO_0_35	G14	BANK35	I/O	U.D.
J1.76	N.C.	Not Connected	-
J1.78	N.C.	Not Connected	-
J1.80	PS_MIO49_501	CPU.PS_MIO49_501	C12	BANK501	I/O	1.8V	Configured as UART1_RX on BELK BSP
J1.82	PS_MIO48_501	CPU.PS_MIO48_501	B12	BANK501	I/O	1.8V	Configured as UART1_TX on BELK BSP
J1.84	PS_MIO47_501	CPU.PS_MIO47_501	B14	BANK501	I/O	1.8V	Internally connected as I2C0_SDA (10K pull-up)
J1.86	DGND	DGND	-		G
J1.88	PS_MIO46_501	CPU.PS_MIO46_501	D16	BANK501	I/O	1.8V	Internally connected as I2C0_CLK (10K pull-up)
J1.90	ETH_INTN	LAN.INT_N / PME_N2	38		O	1.8V	Internal pull-up 4K7 (by default not connected)
J1.92	DGND	DGND	-		G
J1.94	ETH_TXRX3_M	LAN.TXRXM_D	11		D	3.3V
J1.96	ETH_TXRX3_P	LAN.TXRXP_D	10		D	3.3V
J1.98	DGND	DGND	-		G
J1.100	ETH_TXRX2_M	LAN.TXRXM_C	8		D	3.3V
J1.102	ETH_TXRX2_P	LAN.TXRXP_C	7		D	3.3V
J1.104	DGND	DGND	-		G
J1.106	CLK125_NDO	LAN.CLK125_NDO	41		I/O	1.8V
J1.108	N.C.	Not Connected	-
J1.110	N.C.	Not Connected	-
J1.112	DGND	DGND	-		G
J1.114	USBP1	USB.DP	6		D
J1.116	USBM1	USB.DM	5		D
J1.118	DGND	DGND	-		G
J1.120	SPI0_CS0N	CPU.PS_MIO1_500 NOR.CS#	A7 C2	BANK500	I/O	3.3V	Internally connected as NOR chip select (if populated)
J1.122	NAND_CS0/SPI0_CS1	CPU.PS_MIO0_500 NAND.~CE	E6 9	BANK500	I/O	3.3V	Internally connected as NAND chip select (if populated)
J1.124	NAND_IO3	CPU.PS_MIO13_500 NAND.I/O3	E8 32	BANK500	I/O	3.3V	Internally connected as NAND I/O (if populated)
J1.126	NAND_IO4	CPU.PS_MIO9_500 NAND.I/O4	B5 41	BANK500	I/O	3.3V	Internally connected as NAND I/O (if populated)
J1.128	NAND_IO5	CPU.PS_MIO10_500 NAND.I/O5	E9 42	BANK500	I/O	3.3V	Internally connected as NAND I/O (if populated)
J1.130	DGND	DGND	-		G
J1.132	NAND_IO6	CPU.PS_MIO11_500 NAND.I/O6	C6 43	BANK500	I/O	3.3V	Internally connected as NAND I/O (if populated)
J1.134	NAND_IO7	CPU.PS_MIO12_500 NAND.I/O7	D9 44	BANK500	I/O	3.3V	Internally connected as NAND I/O (if populated)
J1.136	NAND_RD_B/VCFG1	CPU.PS_MIO8_500 NAND.~RE	D5 8	BANK500	I/O	3.3V	This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
J1.138	NAND_CLE/VCFG0	CPU.PS_MIO7_500 NAND.CLE	D8 16	BANK500	I/O	3.3V	This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
J1.140	DGND	DGND	-		G

SOM J2 ODD pins (1 to 139) declaration

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J2.1	DGND	DGND	-		G
J2.3	DGND	DGND	-		G
J2.5	IO_L8P_T1_34	FPGA.IO_L8P_T1_34	W14	BANK34	I/O	3.3V
J2.7	IO_L8N_T1_34	FPGA.IO_L8N_T1_34	Y14	BANK34	I/O	3.3V
J2.9	IO_L6P_T0_34	CAN.D FPGA.IO_L6P_T0_34	1 P14	BANK34	I/O	3.3V	By default used as CAN.TX with internal CAN PHY transceiver (mount option)
J2.11	IO_L6N_T0_VREF_34	FPGA.IO_L6N_T0_VREF_34	R14	BANK34	I/O	3.3V
J2.13	DGND	DGND	-		G
J2.15	IO_L3P_T0_DQS_PUDC_B_34	FPGA.IO_L3P_T0_DQS_PUDC_B_34	U13	BANK34	I/O	3.3V	Internal 10K resistor pull-up
J2.17	IO_L3N_T0_DQS_34	FPGA.IO_L3N_T0_DQS_34	V13	BANK34	I/O	3.3V
J2.19	IO_L2P_T0_34	FPGA.IO_L2P_T0_34	T12	BANK34	I/O	3.3V
J2.21	IO_L2N_T0_34	FPGA.IO_L2N_T0_34	U12	BANK34	I/O	3.3V
J2.23	DGND	DGND	-		G
J2.25	IO_L22P_T3_34	FPGA.IO_L22P_T3_34	W18	BANK34	I/O	3.3V
J2.27	IO_L22N_T3_34	FPGA.IO_L22N_T3_34	W19	BANK34	I/O	3.3V
J2.29	IO_L21P_T3_DQS_34	FPGA.IO_L21P_T3_DQS_34	V17	BANK34	I/O	3.3V
J2.31	IO_L21N_T3_DQS_34	FPGA.IO_L21N_T3_DQS_34	V18	BANK34	I/O	3.3V
J2.33	DGND	DGND	-		G
J2.35	IO_L19P_T3_34	CAN.R FPGA.IO_L19P_T3_34	4 R16	BANK34	I/O	3.3V	By default used as CAN.RX with internal CAN PHY transceiver (mount option)
J2.37	IO_L19N_T3_VREF_34	FPGA.IO_L19N_T3_VREF_34	R17	BANK34	I/O	3.3V
J2.39	IO_L18P_T2_34	FPGA.IO_L18P_T2_34	V16	BANK34	I/O	3.3V
J2.41	IO_L18N_T2_34	FPGA.IO_L18N_T2_34	W16	BANK34	I/O	3.3V
J2.43	DGND	DGND	-		G
J2.45	IO_L15P_T2_DQS_34	FPGA.IO_L15P_T2_DQS_34	T20	BANK34	I/O	3.3V
J2.47	IO_L15N_T2_DQS_34	FPGA.IO_L15N_T2_DQS_34	U20	BANK34	I/O	3.3V
J2.49	DGND	DGND	-
J2.51	IO_L13P_T1_MRCC_34	FPGA.IO_L13P_T1_MRCC_34	N18	BANK34	I/O	3.3V
J2.53	IO_L13N_T1_MRCC_34	FPGA.IO_L13N_T1_MRCC_34	P19	BANK34	I/O	3.3V
J2.55	DGND	DGND	-
J2.57	IO_L11P_T1_SRCC_34	FPGA.IO_L11P_T1_SRCC_34	U14	BANK34	I/O	3.3V
J2.59	IO_L11N_T1_SRCC_34	FPGA.IO_L11N_T1_SRCC_34	U15	BANK34	I/O	3.3V
J2.61	DGND	DGND	-
J2.63	IO_L10P_T1_34	FPGA.IO_L10P_T1_34	V15	BANK34	I/O	3.3V
J2.65	IO_L10N_T1_34	FPGA.IO_L10N_T1_34	W15	BANK34	I/O	3.3V
J2.67	IO_25_34	FPGA.IO_25_34	T19	BANK34	I/O	3.3V
J2.69	IO_0_34	FPGA.IO_0_34	R19	BANK34	I/O	3.3V
J2.71	DGND	DGND	-		G
J2.73	N.C.	Not Connected	-
J2.75	N.C.	Not Connected	-
J2.77	N.C.	Not Connected	-
J2.79	N.C.	Not Connected	-
J2.81	N.C.	Not Connected	-
J2.83	N.C.	Not Connected	-
J2.85	N.C.	Not Connected	-
J2.87	N.C.	Not Connected	-
J2.89	N.C.	Not Connected	-
J2.91	N.C.	Not Connected	-
J2.93	RTC_32KHZ	RTC.32KHZ	1		O	3.3V	It can be left open if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
J2.95	RTC_RST	RTC.~RST	4		I/O	3.3V	It can be left open if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
J2.97	XADC_VN_R	FPGA.VN_0	L10		A / I	VREFP	See BELK-TN-012 Using XADC signal module
J2.99	XADC_VP_R	FPGA.VP_0	K9		A / I	VREFP	See BELK-TN-012 Using XADC signal module
J2.101	N.C.	Not Connected	-
J2.103	CONN_SPI_RSTn	NOR.~RESET/RFU	A4			3.3V
J2.105	CAN_L	CAN.L	6		I/O	3.3V	For further details, please refer to the Texas Instruments SN65HVD232 datasheet.
J2.107	CAN_H	CAN.H	7		I/O	3.3V	For further details, please refer to the Texas Instruments SN65HVD232 datasheet.
J2.109	DGND	DGND	-		G
J2.111	RTC_INT/SQW	RTC.RTC_INT/SQW	3		I/O	3.3V	It can be left open if not used. When used, a proper pull-up resistor is required on the carrier board. For further details, please refer to the Maxim Integrated DS3232 datasheet.
J2.113	RTC_VBAT	RTC.VBAT	6		S	3.0V	Connect to ground if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
J2.115	VBAT	CPU.VCCBATT_0	F11		S		This pin is connected to the VCCBATT_0 (for the battery-backed RAM - BBRAM) pin of the Zynq SOC. For additional information, please refer to the Zynq datasheet and TRM.
J2.117	DGND	DGND	-		G
J2.119	3.3VIN	+3.3 V	-		S
J2.121	3.3VIN	+3.3 V	-		S
J2.123	3.3VIN	+3.3 V	-		S
J2.125	DGND	DGND	-		G
J2.127	3.3VIN	+3.3 V	-		S
J2.129	3.3VIN	+3.3 V	-		S
J2.131	3.3VIN	+3.3 V	-		S
J2.133	3.3VIN	+3.3 V	-		S
J2.135	3.3VIN	+3.3 V	-		S
J2.137	3.3VIN	+3.3 V	-		S
J2.139	DGND	DGND	-		G

SOM J2 EVEN pins (2 to 140) declaration

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J2.2	DGND	DGND	-		G
J2.4	IO_L9P_T1_DQS_34	FPGA.IO_L9P_T1_DQS_34	T16	BANK34	I/O	3.3V
J2.6	IO_L9N_T1_DQS_34	FPGA.IO_L9N_T1_DQS_34	U17	BANK34	I/O	3.3V
J2.8	IO_L7P_T1_34	FPGA.IO_L7P_T1_34	Y16	BANK34	I/O	3.3V
J2.10	IO_L7N_T1_34	FPGA.IO_L7N_T1_34	Y17	BANK34	I/O	3.3V
J2.12	DGND	DGND	-		G
J2.14	IO_L5P_T0_34	FPGA.IO_L5P_T0_34	T14	BANK34	I/O	3.3V
J2.16	IO_L5N_T0_34	FPGA.IO_L5N_T0_34	T15	BANK34	I/O	3.3V
J2.18	IO_L4P_T0_34	FPGA.IO_L4P_T0_34	V12	BANK34	I/O	3.3V
J2.20	IO_L4N_T0_34	FPGA.IO_L4N_T0_34	W13	BANK34	I/O	3.3V
J2.22	DGND	DGND	-		G
J2.24	IO_L24P_T3_34	FPGA.IO_L24P_T3_34	P15	BANK34	I/O	3.3V
J2.26	IO_L24N_T3_34	FPGA.IO_L24N_T3_34	P16	BANK34	I/O	3.3V
J2.28	IO_L23P_T3_34	FPGA.IO_L23P_T3_34	N17	BANK34	I/O	3.3V
J2.30	IO_L23N_T3_34	FPGA.IO_L23N_T3_34	P18	BANK34	I/O	3.3V
J2.32	DGND	DGND	-		G
J2.34	IO_L20P_T3_34	FPGA.IO_L20P_T3_34	T17	BANK34	I/O	3.3V
J2.36	IO_L20N_T3_34	FPGA.IO_L20N_T3_34	R18	BANK34	I/O	3.3V
J2.38	IO_L1P_T0_34	FPGA.IO_L1P_T0_34	T11	BANK34	I/O	3.3V
J2.40	IO_L1N_T0_34	FPGA.IO_L1N_T0_34	T10	BANK34	I/O	3.3V
J2.42	DGND	DGND	-		G
J2.44	IO_L17P_T2_34	FPGA.IO_L17P_T2_34	Y18	BANK34	I/O	3.3V
J2.46	IO_L17N_T2_34	FPGA.IO_L17N_T2_34	Y19	BANK34	I/O	3.3V
J2.48	IO_L16P_T2_34	FPGA.IO_L16P_T2_34	V20	BANK34	I/O	3.3V
J2.50	IO_L16N_T2_34	FPGA.IO_L16N_T2_34	W20	BANK34	I/O	3.3V
J2.52	DGND	DGND	-		G
J2.54	IO_L14P_T2_SRCC_34	FPGA.IO_L14P_T2_SRCC_34	N20	BANK34	I/O	3.3V
J2.56	IO_L14N_T2_SRCC_34	FPGA.IO_L14N_T2_SRCC_34	P20	BANK34	I/O	3.3V
J2.58	DGND	DGND	-		G
J2.60	IO_L12P_T1_MRCC_34	FPGA.IO_L12P_T1_MRCC_34	U18	BANK34	I/O	3.3V
J2.62	IO_L12N_T1_MRCC_34	FPGA.IO_L12N_T1_MRCC_34	U19	BANK34	I/O	3.3V
J2.64	DGND	DGND	-		G
J2.66	N.C.	Not Connected	-
J2.68	N.C.	Not Connected	-
J2.70	N.C.	Not Connected	-
J2.72	N.C.	Not Connected	-
J2.74	N.C.	Not Connected	-
J2.76	N.C.	Not Connected	-
J2.78	N.C.	Not Connected	-
J2.80	JTAG_TDO	CPU.TDO_0	F6
J2.82	JTAG_TDI	CPU.TDI_0	G6
J2.84	JTAG_TMS	CPU.TMS_0	J6
J2.86	JTAG_TCK	CPU.TCK_0	F9
J2.88	DGND	DGND	-		G
J2.90	FPGA_INIT_B	FPGA.INIT_B_0	R10				For further details, please refer to PL initialization signals
J2.92	FPGA_PROGRAM_B	FPGA.PROGRAM_B_0	L6				For further details, please refer to PL initialization signals (10 kΩ pull-up resistor is already mounted on BORA module)
J2.94	FPGA_DONE	FPGA.DONE_0	R11				For further details, please refer to PL initialization signals
J2.96	WD_SET2	WDT.SET2	6		I	3.3V	Internal 10K pull-up. For further details, please refer to the Maxim Integrated MAX6373 datasheet.
J2.98	WD_SET1	WDT.SET1	5		I	3.3V	Internal 10K pull-up. For further details, please refer to the Maxim Integrated MAX6373 datasheet.
J2.100	WD_SET0	WDT.SET0	4		I	3.3V	Internal 10K pull-down. For further details, please refer to the Maxim Integrated MAX6373 datasheet.
J2.102	DGND	DGND	-		G
J2.104	PS_MIO50_501	CPU.PS_MIO50_501 USBOTG.RESETB	B13 22	BANK501	I/O	1.8V	For further details, please refer to Reset_scheme_(Bora)#PS_MIO50_501
J2.106	PS_MIO51_501	CPU.PS_MIO51_501 ETHPHY1GB.RESET_N	B9 42	BANK501	I/O	1.8V	For further details, please refer to Reset_scheme_(Bora)#PS_MIO51_501
J2.108	BOARD_PGOOD	PSUSWITCHFPGABANK13.ON PSUSWITCHFPGABANK35.ON PSUSWITCHFPGABANK500/34.ON PSUSWITCHFPGABANK501.ON DDRVREFREGULATOR.PGOOD	3 3 3 3 9		O	3.3V	For further details, please refer to Power Supply (Bora)
J2.110	CB_PWR_GOOD	1V0REGULATOR.ENABLE	-		I	3.3V	For further details, please refer to Power Supply (Bora)
J2.112	SYS_RSTN	CPU.PS_SRST_B_501 MTR.~RST	B10 5		I	1.8V	For further details, please refer to Reset signals
J2.114	PORSTN	CPU.PS_POR_B_500	C7		I/O	3.3V	For further details, please refer to Reset signals
J2.116	MRSTN	MTR.MR	6		I	3.3V	For further details, please refer to Reset signals
J2.118	DGND	DGND	-		G
J2.120	3.3VIN	+3.3 V	-		S
J2.122	3.3VIN	+3.3 V	-		S
J2.124	DGND	DGND	-		G
J2.126	3.3VIN	+3.3 V	-		S
J2.128	3.3VIN	+3.3 V	-		S
J2.130	3.3VIN	+3.3 V	-		S
J2.132	3.3VIN	+3.3 V	-		S
J2.134	3.3VIN	+3.3 V	-		S
J2.136	3.3VIN	+3.3 V	-		S
J2.138	3.3VIN	+3.3 V	-		S
J2.140	DGND	DGND	-		G

SOM J3 ODD pins (1 to 139)declaration

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J3.1	N.C.	Not Connected	-
J3.3	N.C.	Not Connected	-
J3.5	N.C.	Not Connected	-
J3.7	N.C.	Not Connected	-
J3.9	N.C.	Not Connected	-
J3.11	N.C.	Not Connected	-
J3.13	N.C.	Not Connected	-
J3.15	N.C.	Not Connected	-
J3.17	N.C.	Not Connected	-
J3.19	N.C.	Not Connected	-
J3.21	N.C.	Not Connected	-
J3.23	N.C.	Not Connected	-
J3.25	N.C.	Not Connected	-
J3.27	N.C.	Not Connected	-
J3.29	N.C.	Not Connected	-
J3.31	N.C.	Not Connected	-
J3.33	N.C.	Not Connected	-
J3.35	N.C.	Not Connected	-
J3.37	N.C.	Not Connected	-
J3.39	N.C.	Not Connected	-
J3.41	N.C.	Not Connected	-
J3.43	N.C.	Not Connected	-
J3.45	N.C.	Not Connected	-
J3.47	N.C.	Not Connected	-
J3.49	N.C.	Not Connected	-
J3.51	N.C.	Not Connected	-
J3.53	N.C.	Not Connected	-
J3.55	N.C.	Not Connected	-
J3.57	N.C.	Not Connected	-
J3.59	N.C.	Not Connected	-
J3.61	N.C.	Not Connected	-
J3.63	N.C.	Not Connected	-
J3.65	N.C.	Not Connected	-
J3.67	DGND	DGND	-
J3.69	N.C.	Not Connected	-
J3.71	N.C.	Not Connected	-
J3.73	N.C.	Not Connected	-
J3.75	N.C.	Not Connected	-
J3.77	N.C.	Not Connected	-
J3.79	N.C.	Not Connected	-
J3.81	N.C.	Not Connected	-
J3.83	N.C.	Not Connected	-
J3.85	N.C.	Not Connected	-
J3.87	N.C.	Not Connected	-
J3.89	N.C.	Not Connected	-
J3.91	N.C.	Not Connected	-
J3.93	DGND	DGND	-		G
J3.95	VDDIO_BANK13	FPGA.VCCO_13	T8 U11 W7 Y10	BANK13	S		N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in Programmable_logic_(Bora).
J3.97	VDDIO_BANK13	FPGA.VCCO_13	T8 U11 W7 Y10	BANK13	S		N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in Programmable_logic_(Bora).
J3.99	VDDIO_BANK13	FPGA.VCCO_13	T8 U11 W7 Y10	BANK13	S		N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in Programmable_logic_(Bora).
J3.101	DGND	DGND	-		G
J3.103	DGND	DGND	-		G
J3.105	IO_L21P_T3_DQS_13	FPGA.IO_L21P_T3_DQS_13	V11	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.107	IO_L21N_T3_DQS_13	FPGA.IO_L21N_T3_DQS_13	V10	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.109	DGND	DGND	-		G
J3.111	IO_L19P_T3_13	FPGA.IO_L19P_T3_13	T5	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.113	IO_L19N_T3_VREF_13	FPGA.IO_L19N_T3_VREF_13	U5	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.115	DGND	DGND	-		G
J3.117	IO_L18P_T2_13	FPGA.IO_L18P_T2_13	W11	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.119	IO_L18N_T2_13	FPGA.IO_L18N_T2_13	Y11	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.121	DGND	DGND	-		G
J3.123	IO_L16P_T2_13	FPGA.IO_L16P_T2_13	W10	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.125	IO_L16N_T2_13	FPGA.IO_L16N_T2_13	W9	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.127	DGND	DGND	-		G
J3.129	IO_L14P_T2_SRCC_13	FPGA.IO_L14P_T2_SRCC_13	Y9	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.131	IO_L14N_T2_SRCC_13	FPGA.IO_L14N_T2_SRCC_13	Y8	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.133	DGND	DGND	-		G
J3.135	IO_L12P_T1_MRCC_13	FPGA.IO_L12P_T1_MRCC_13	T9	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.137	IO_L12N_T1_MRCC_13	FPGA.IO_L12N_T1_MRCC_13	U10	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.139	DGND	DGND	-		G

SOM J3 EVEN pins (2 to 140) declaration

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J3.2	N.C.	Not Connected	-
J3.4	N.C.	Not Connected	-
J3.6	N.C.	Not Connected	-
J3.8	N.C.	Not Connected	-
J3.10	N.C.	Not Connected	-
J3.12	N.C.	Not Connected	-
J3.14	N.C.	Not Connected	-
J3.16	N.C.	Not Connected	-
J3.18	N.C.	Not Connected	-
J3.20	N.C.	Not Connected	-
J3.22	N.C.	Not Connected	-
J3.24	N.C.	Not Connected	-
J3.26	N.C.	Not Connected	-
J3.28	N.C.	Not Connected	-
J3.30	N.C.	Not Connected	-
J3.32	N.C.	Not Connected	-
J3.34	N.C.	Not Connected	-
J3.36	N.C.	Not Connected	-
J3.38	N.C.	Not Connected	-
J3.40	N.C.	Not Connected	-
J3.42	N.C.	Not Connected	-
J3.44	N.C.	Not Connected	-
J3.46	N.C.	Not Connected	-
J3.48	N.C.	Not Connected	-
J3.50	N.C.	Not Connected	-
J3.52	N.C.	Not Connected	-
J3.54	N.C.	Not Connected	-
J3.56	N.C.	Not Connected	-
J3.58	N.C.	Not Connected	-
J3.60	N.C.	Not Connected	-
J3.62	N.C.	Not Connected	-
J3.64	N.C.	Not Connected	-
J3.66	N.C.	Not Connected	-
J3.68	DGND	DGND	-		G
J3.70	N.C.	Not Connected	-
J3.72	MON_VCCPLL	n.a.	-				By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
J3.74	MON_XADC_VCC	n.a.	-				By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
J3.76	MON_FPGA_VDDIO_BANK35	n.a.	-				By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
J3.78	MON_FPGA_VDDIO_BANK34	n.a.	-				By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
J3.80	MON_FPGA_VDDIO_BANK13	n.a.	-				By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
J3.82	MON_1.8V_IO	n.a.	-				By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
J3.84	MON_3.3V	n.a.	-				By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
J3.86	MON_1V2_ETH	n.a.	-				By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
J3.88	MON_VDDQ_1V5	n.a.	-				By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
J3.90	MON_1.8V	n.a.	-				By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
J3.92	MON_1.0V	n.a.	-				By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
J3.94	DGND	DGND	-		G
J3.96	VDDIO_BANK13	FPGA.VCCO_13	T8 U11 W7 Y10	BANK13	S		N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in Programmable_logic_(Bora).
J3.98	VDDIO_BANK13	FPGA.VCCO_13	T8 U11 W7 Y10	BANK13	S		N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in Programmable_logic_(Bora).
J3.100	IO_L6N_T0_VREF_13	FPGA.IO_L6N_T0_VREF_13	V5	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.102	DGND	DGND	-		G
J3.104	IO_L22P_T3_13	FPGA.IO_L22P_T3_13	V6	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.106	IO_L22N_T3_13	FPGA.IO_L22N_T3_13	W6	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.108	DGND	DGND	-		G
J3.110	IO_L20P_T3_13	FPGA.IO_L20P_T3_13	Y12	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.112	IO_L20N_T3_13	FPGA.IO_L20N_T3_13	Y13	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.114	DGND	DGND	-		G
J3.116	IO_L17P_T2_13	FPGA.IO_L17P_T2_13	U9	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.118	IO_L17N_T2_13	FPGA.IO_L17N_T2_13	U8	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.120	DGND	DGND	-		G
J3.122	IO_L15P_T2_DQS_13	FPGA.IO_L15P_T2_DQS_13	V8	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.124	IO_L15N_T2_DQS_13	FPGA.IO_L15N_T2_DQS_13	W8	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.126	DGND	DGND	-		G
J3.128	IO_L13P_T2_MRCC_13	FPGA.IO_L13P_T2_MRCC_13	Y7	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.130	IO_L13N_T2_MRCC_13	FPGA.IO_L13N_T2_MRCC_13	Y6	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.132	DGND	DGND	-		G
J3.134	IO_L11P_T1_SRCC_13	FPGA.IO_L11P_T1_SRCC_13	U7	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.136	IO_L11N_T1_SRCC_13	FPGA.IO_L11N_T1_SRCC_13	V7	BANK13	I/O	U.D.	Not available on Bora SOMs equipped with the XC7Z010 SOC
J3.138	DGND	DGND	-		G
J3.140	DGND	DGND	-		G