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Pinout (Bora)

45 bytes added, 08:51, 1 December 2017
minor change
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;" align="center"|'''Pin'''| align="center" style="background:#f0f0f0;" align="center"|'''Pin Name'''| align="center" style="background:#f0f0f0;" align="center"|'''Internal Connections'''| align="center" style="background:#f0f0f0;" align="center"|'''Ball/pin #'''| align="center" style="background:#f0f0f0;" align="center"|'''Supply Group'''| align="center" style="background:#f0f0f0;" align="center"|'''Type'''| align="center" style="background:#f0f0f0;" align="center"|'''Voltage'''| align="center" style="background:#f0f0f0;" align="center"|'''Note'''
|-
|J1.1||DGND||DGND||n.a.||||||||
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;" align="center"|'''Pin'''| align="center" style="background:#f0f0f0;" align="center"|'''Pin Name'''| align="center" style="background:#f0f0f0;" align="center"|'''Internal Connections'''| align="center" style="background:#f0f0f0;" align="center"|'''Ball/pin #'''| align="center" style="background:#f0f0f0;" align="center"|'''Supply Group'''| align="center" style="background:#f0f0f0;" align="center"|'''Type'''| align="center" style="background:#f0f0f0;" align="center"|'''Voltage'''| align="center" style="background:#f0f0f0;" align="center"|'''Note'''
|-
|J1.2||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||
|J1.134||NAND_IO7||CPU.PS_MIO12_500<br>NAND.I/O7||D9<br>44||||||||
|-
|J1.136||NAND_RD_B/VCFG1||CPU.PS_MIO8_500<br>NAND.~RE||D5<br>8|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
|J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500<br>NAND.CLE||D8<br>16|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
|J1.140||DGND||DGND||n.a.||||||||
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;" align="center"|'''Pin'''| align="center" style="background:#f0f0f0;" align="center"|'''Pin Name'''| align="center" style="background:#f0f0f0;" align="center"|'''Internal Connections'''| align="center" style="background:#f0f0f0;" align="center"|'''Ball/pin #'''| align="center" style="background:#f0f0f0;" align="center"|'''Supply Group'''| align="center" style="background:#f0f0f0;" align="center"|'''Type'''| align="center" style="background:#f0f0f0;" align="center"|'''Voltage'''| align="center" style="background:#f0f0f0;" align="center"|'''Note'''
|-
|J2.1||DGND||DGND||n.a.||||||||
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;" align="center"|'''Pin'''| align="center" style="background:#f0f0f0;" align="center"|'''Pin Name'''| align="center" style="background:#f0f0f0;" align="center"|'''Internal Connections'''| align="center" style="background:#f0f0f0;" align="center"|'''Ball/pin #'''| align="center" style="background:#f0f0f0;" align="center"|'''Supply Group'''| align="center" style="background:#f0f0f0;" align="center"|'''Type'''| align="center" style="background:#f0f0f0;" align="center"|'''Voltage'''| align="center" style="background:#f0f0f0;" align="center"|'''Note'''
|-
|J2.2||DGND||DGND||n.a.||||||||
|J2.104||PS_MIO50_501||CPU.PS_MIO50_501<br>USBOTG.RESETB||B13<br>22|||||||| For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(Bora)#PS_MIO50_501]]
|-
|J2.106||PS_MIO51_501||CPU.PS_MIO51_501<br>ETHPHY1GB.RESET_N||B9<br>42|||||||| For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO51_501_.28J2.106.29 | Reset_scheme_(Bora)#PS_MIO51_501 ]]
|-
|J2.108||BOARD_PGOOD||PSUSWITCHFPGABANK13.ON<br>PSUSWITCHFPGABANK35.ON<br>PSUSWITCHFPGABANK500/34.ON<br>PSUSWITCHFPGABANK501.ON<br>DDRVREFREGULATOR.PGOOD||3<br>3<br>3<br>3<br>9||||||||
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;" align="center"|'''Pin'''| align="center" style="background:#f0f0f0;" align="center"|'''Pin Name'''| align="center" style="background:#f0f0f0;" align="center"|'''Internal Connections'''| align="center" style="background:#f0f0f0;" align="center"|'''Ball/pin #'''| align="center" style="background:#f0f0f0;" align="center"|'''Supply Group'''| align="center" style="background:#f0f0f0;" align="center"|'''Type'''| align="center" style="background:#f0f0f0;" align="center"|'''Voltage'''| align="center" style="background:#f0f0f0;" align="center"|'''Note'''
|-
|J3.1||N.C.||Not Connected||n.a.||||||||
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;" align="center"|'''Pin'''| align="center" style="background:#f0f0f0;" align="center"|'''Pin Name'''| align="center" style="background:#f0f0f0;" align="center"|'''Internal Connections'''| align="center" style="background:#f0f0f0;" align="center"|'''Ball/pin #'''| align="center" style="background:#f0f0f0;" align="center"|'''Supply Group'''| align="center" style="background:#f0f0f0;" align="center"|'''Type'''| align="center" style="background:#f0f0f0;" align="center"|'''Voltage'''| align="center" style="background:#f0f0f0;" align="center"|'''Note'''
|-
|J3.2||N.C.||Not Connected||n.a.||||||||
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