Changes

Pinout (Bora)

6,674 bytes added, 09:00, 1 December 2017

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{| class="wikitable" {| {{table}}

|-

|J1.1||DGND||DGND||n.a.||||||||

|J1.131||NAND_BUSY||CPU.PS_MIO14_500||C5||||||||

|-

|J1.133||PS_MIO15_500||CPU.PS_MIO15_500 WDT.WDI||C8 1||||||||See also [[Watchdog_(Bora)|this page]]

|-

|J1.135||N.C.||Not Connected||n.a.||||||||

{| class="wikitable" {| {{table}}

|-

|J1.2||VDDIO_BANK35||FPGA.VCCO_35||C19 F18 H14 J17 K20 M16||||||||

|J1.134||NAND_IO7||CPU.PS_MIO12_500 NAND.I/O7||D9 44||||||||

|-

|J1.136||NAND_RD_B/VCFG1||CPU.PS_MIO8_500 NAND.~RE||D5 8|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.

|-

|J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500 NAND.CLE||D8 16|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.

|-

|J1.140||DGND||DGND||n.a.||||||||

{| class="wikitable" {| {{table}}

|-

|J2.1||DGND||DGND||n.a.||||||||

|J2.109||DGND||DGND||n.a.||||||||

|-

|J2.111||RTC_INT/SQW||RTC.RTC_INT/SQW||3|||||||| It can be left open if not used. When used, a proper pull-up resistor is required on the carrier board. For further details, please refer to the Maxim Integrated DS3232 datasheet.

|-

|J2.113||RTC_VBAT||RTC.VBAT||6||||||||

|-

|J2.115||VBAT||CPU.VCCBATT_0||F11||||||||This pin is connected to the VCCBATT_0 (for the battery-backed RAM - BBRAM) pin of the Zynq SOC. For additional information, please refer to the Zynq datasheet and TRM.

|-

|J2.117||DGND||DGND||n.a.||||||||

{| class="wikitable" {| {{table}}

|-

|J2.2||DGND||DGND||n.a.||||||||

|J2.88||DGND||DGND||n.a.||||||||

|-

|J2.90||FPGA_INIT_B||FPGA.INIT_B_0||R10||||||||Place external 4.7 kΩ (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]

|-

|J2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||L6||||||||Place external 4.7 kΩ (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supply For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration] (10 kΩ pull-up resistor is already mounted on BORA module)

|-

|J2.94||FPGA_DONE||FPGA.DONE_0||R11||||||||Place external 300Ω pull-up resistor to BOARD_PGOOD driven +3.3V supply For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]

|-

|J2.96||WD_SET2||WDT.SET2||6||||||||

|J2.104||PS_MIO50_501||CPU.PS_MIO50_501 USBOTG.RESETB||B13 22|||||||| For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(Bora)#PS_MIO50_501]]

|-

|J2.106||PS_MIO51_501||CPU.PS_MIO51_501 ETHPHY1GB.RESET_N||B9 42|||||||| For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO51_501_.28J2.106.29 | Reset_scheme_(Bora)#PS_MIO51_501 ]]

|-

|J2.108||BOARD_PGOOD||PSUSWITCHFPGABANK13.ON PSUSWITCHFPGABANK35.ON PSUSWITCHFPGABANK500/34.ON PSUSWITCHFPGABANK501.ON DDRVREFREGULATOR.PGOOD||3 3 3 3 9||||||||

{| class="wikitable" {| {{table}}

|-

|J3.1||N.C.||Not Connected||n.a.||||||||

|J3.93||DGND||DGND||n.a.||||||||

|-

|J3.95||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10||||||||N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].

|-

|J3.97||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10||||||||N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].

|-

|J3.99||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10||||||||N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].

|-

|J3.101||DGND||DGND||n.a.||||||||

|J3.103||DGND||DGND||n.a.||||||||

|-

|J3.105||IO_L21P_T3_DQS_13||FPGA.IO_L21P_T3_DQS_13||V11||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.107||IO_L21N_T3_DQS_13||FPGA.IO_L21N_T3_DQS_13||V10||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.109||DGND||DGND||n.a.||||||||

|-

|J3.111||IO_L19P_T3_13||FPGA.IO_L19P_T3_13||T5||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.113||IO_L19N_T3_VREF_13||FPGA.IO_L19N_T3_VREF_13||U5||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.115||DGND||DGND||n.a.||||||||

|-

|J3.117||IO_L18P_T2_13||FPGA.IO_L18P_T2_13||W11||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.119||IO_L18N_T2_13||FPGA.IO_L18N_T2_13||Y11||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

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|J3.121||DGND||DGND||n.a.||||||||

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|J3.123||IO_L16P_T2_13||FPGA.IO_L16P_T2_13||W10||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.125||IO_L16N_T2_13||FPGA.IO_L16N_T2_13||W9||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.127||DGND||DGND||n.a.||||||||

|-

|J3.129||IO_L14P_T2_SRCC_13||FPGA.IO_L14P_T2_SRCC_13||Y9||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.131||IO_L14N_T2_SRCC_13||FPGA.IO_L14N_T2_SRCC_13||Y8||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.133||DGND||DGND||n.a.||||||||

|-

|J3.135||IO_L12P_T1_MRCC_13||FPGA.IO_L12P_T1_MRCC_13||T9||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.137||IO_L12N_T1_MRCC_13||FPGA.IO_L12N_T1_MRCC_13||U10||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.139||DGND||DGND||n.a.||||||||

{| class="wikitable" {| {{table}}

|-

|J3.2||N.C.||Not Connected||n.a.||||||||

|J3.70||N.C.||Not Connected||n.a.||||||||

|-

|J3.72||MON_VCCPLL||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.74||MON_XADC_VCC||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.76||MON_FPGA_VDDIO_BANK35||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.78||MON_FPGA_VDDIO_BANK34||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.80||MON_FPGA_VDDIO_BANK13||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.82||MON_1.8V_IO||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.84||MON_3.3V||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.86||MON_1V2_ETH||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.88||MON_VDDQ_1V5||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.90||MON_1.8V||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.92||MON_1.0V||n.a.||n.a.||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.

|-

|J3.94||DGND||DGND||n.a.||||||||

|-

|J3.96||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10||||||||N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].

|-

|J3.98||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10||||||||N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].

|-

|J3.100||IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||V5||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.102||DGND||DGND||n.a.||||||||

|-

|J3.104||IO_L22P_T3_13||FPGA.IO_L22P_T3_13||V6||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.106||IO_L22N_T3_13||FPGA.IO_L22N_T3_13||W6||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.108||DGND||DGND||n.a.||||||||

|-

|J3.110||IO_L20P_T3_13||FPGA.IO_L20P_T3_13||Y12||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.112||IO_L20N_T3_13||FPGA.IO_L20N_T3_13||Y13||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.114||DGND||DGND||n.a.||||||||

|-

|J3.116||IO_L17P_T2_13||FPGA.IO_L17P_T2_13||U9||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.118||IO_L17N_T2_13||FPGA.IO_L17N_T2_13||U8||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.120||DGND||DGND||n.a.||||||||

|-

|J3.122||IO_L15P_T2_DQS_13||FPGA.IO_L15P_T2_DQS_13||V8||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.124||IO_L15N_T2_DQS_13||FPGA.IO_L15N_T2_DQS_13||W8||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.126||DGND||DGND||n.a.||||||||

|-

|J3.128||IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y7||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.130||IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y6||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.132||DGND||DGND||n.a.||||||||

|-

|J3.134||IO_L11P_T1_SRCC_13||FPGA.IO_L11P_T1_SRCC_13||U7||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.136||IO_L11N_T1_SRCC_13||FPGA.IO_L11N_T1_SRCC_13||V7||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC

|-

|J3.138||DGND||DGND||n.a.||||||||

U0004

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