Changes

|J2.2||DGND||DGND||n.a.-||-||G||-||Digital ground

|J2.4||IO_L9P_T1_DQS_34||FPGA.IO_L9P_T1_DQS_34||T16J3||Bank 34||I/O||User defined||

|J2.6||IO_L9N_T1_DQS_34||FPGA.IO_L9N_T1_DQS_34||U17K2||Bank 34||I/O||User defined||

|J2.8||IO_L7P_T1_34||FPGA.IO_L7P_T1_34||Y16J5||Bank 34||I/O||User defined||

|J2.10||IO_L7N_T1_34||FPGA.IO_L7N_T1_34||Y17K5||Bank 34||I/O||User defined||

|J2.12||DGND||DGND||n.a.-||-||G||-||Digital ground

|J2.14||IO_L5P_T0_34||FPGA.IO_L5P_T0_34||T14N8||Bank 34||I/O||User defined||

|J2.16||IO_L5N_T0_34||FPGA.IO_L5N_T0_34||T15P8||Bank 34||I/O||User defined||

|J2.18||IO_L4P_T0_34||FPGA.IO_L4P_T0_34||V12L6||Bank 34||I/O||User defined||

|J2.20||IO_L4N_T0_34||FPGA.IO_L4N_T0_34||W13M6||Bank 34||I/O||User defined||

|J2.22||DGND||DGND||n.a.-||-||G||-||Digital ground

|J2.24||IO_L24P_T3_34||FPGA.IO_L24P_T3_34||P15P7||Bank 34||I/O||User defined||

|J2.26||IO_L24N_T3_34||FPGA.IO_L24N_T3_34||P16R7||Bank 34||I/O||User defined||

|J2.28||IO_L23P_T3_34||FPGA.IO_L23P_T3_34||N17R5||Bank 34||I/O||User defined||

|J2.30||IO_L23N_T3_34||FPGA.IO_L23N_T3_34||P18R4||Bank 34||I/O||User defined||

|J2.32||DGND||DGND||n.a.-||-||G||-||Digital ground

|J2.34||IO_L20P_T3_34||FPGA.IO_L20P_T3_34||T17P6||Bank 34||I/O||User defined||

|J2.36||IO_L20N_T3_34||FPGA.IO_L20N_T3_34||R18P5||Bank 34||I/O||User defined||

|J2.38||IO_L1P_T0_34||FPGA.IO_L1P_T0_34||T11J8||Bank 34||I/O||User defined||

|J2.40||IO_L1N_T0_34||FPGA.IO_L1N_T0_34||T10K8||Bank 34||I/O||User defined||

|J2.42||DGND||DGND||n.a.-||-||G||-||Digital ground

|J2.44||IO_L17P_T2_34||FPGA.IO_L17P_T2_34||Y18R3||Bank 34||I/O||User defined||

|J2.46||IO_L17N_T2_34||FPGA.IO_L17N_T2_34||Y19R2||Bank 34||I/O||User defined||

|J2.48||IO_L16P_T2_34||FPGA.IO_L16P_T2_34||V20N1||Bank 34||I/O||User defined||

|J2.50||IO_L16N_T2_34||FPGA.IO_L16N_T2_34||W20P1||Bank 34||I/O||User defined||

|J2.52||DGND||DGND||n.a.-||-||G||-||Digital ground

|J2.54||IO_L14P_T2_SRCC_34||FPGA.IO_L14P_T2_SRCC_34||N20U2||Bank 34||I/O||User defined||

|J2.56||IO_L14N_T2_SRCC_34||FPGA.IO_L14N_T2_SRCC_34||P20U1||Bank 34||I/O||User defined||

|J2.58||DGND||DGND||n.a.-||-||G||-||Digital ground

|J2.60||IO_L12P_T1_MRCC_34||FPGA.IO_L12P_T1_MRCC_34||U18L5||Bank 34||I/O||User defined||

|J2.62||IO_L12N_T1_MRCC_34||FPGA.IO_L12N_T1_MRCC_34||U19L4||Bank 34||I/O||User defined||

|J2.64||DGND||DGND||n.a.-||-||G||-||Digital ground

|J2.66||N.C.VDDIO_BANK34||Not ConnectedFPGA.VCCO_34||n.a.K6H2L3N7P4R1||Bank 34||S||User defined||Bank34 I/O Power Supply

|J2.68||N.C.VDDIO_BANK34||Not ConnectedFPGA.VCCO_34||n.a.K6H2L3N7P4R1||Bank 34||S||User defined||Bank34 I/O Power Supply

|J2.70||N.C.VDDIO_BANK34||Not ConnectedFPGA.VCCO_34||n.a.K6H2L3N7P4R1||Bank 34||S||User defined||Bank34 I/O Power Supply

|J2.72||N.C.VDDIO_BANK34||Not ConnectedFPGA.VCCO_34||n.a.K6H2L3N7P4R1||Bank 34||S||User defined||Bank34 I/O Power Supply

|J2.74||N.C.RFU||Not Connected-||n.a.-||-||-||-||Reserved for future use. Must be left floating.

|J2.76||N.C.RFU||Not Connected-||n.a.-||-||-||-||Reserved for future use. Must be left floating.

|J2.78||N.C.RFU||Not Connected-||n.a.-||-||-||-||Reserved for future use. Must be left floating.

|J2.80||JTAG_TDO||CPU.TDO_0||F6G9||BANK 0||O||3.3V||

|J2.82||JTAG_TDI||CPU.TDI_0||G6H9||BANK 0||I||3.3V||

|J2.84||JTAG_TMS||CPU.TMS_0||J6H10||BANK 0||I||3.3V||

|J2.86||JTAG_TCK||CPU.TCK_0||F9H11||BANK 0||I||3.3V||

|J2.88||DGND||DGND||n.a.-||-||G||-||Digital ground

|J2.90||FPGA_INIT_B||FPGA.INIT_B_0||R10T8||BANK 0||I/O||3.3V||

|J2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||L6V10||BANK 0||I||3.3V||

|J2.94||FPGA_DONE||FPGA.DONE_0DONE0||R11T10||BANK 0||I/O||3.3V||

|J2.96||WD_SET2||WDT.SET2||6||3.3V||I||3.3V||

|J2.98||WD_SET1||WDT.SET1||5||3.3V||I||3.3V||

|J2.100||WD_SET0||WDT.SET0||4||3.3V||I||3.3V||

|J2.102||DGND||DGND||n.a.-||-||G||-||Digital ground

|J2.104||PS_MIO50_501||CPU.PS_MIO50_501<br>USBOTG.RESETB||B13<br>D1022||BANK 501||I/O||1.8V|| For further details, please refer to [[Reset_scheme_(BoraBoraXpress)#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(BoraBoraXpress)#PS_MIO50_501]]

|J2.106||PS_MIO51_501||CPU.PS_MIO51_501<br>ETHPHY1GB.RESET_N||B9<br>C1342||BANK 501||I/O||1.8V|| For further details, please refer to [[Reset_scheme_(BoraBoraXpress)#PS_MIO51_501_.28J2.106.29 | Reset_scheme_(BoraBoraXpress)#PS_MIO51_501 ]]

|J2.108||BOARD_PGOODSOM_PGOOD||PSUSWITCHFPGABANK13SOM_PGOOD_LOGIC.ON<br>PSUSWITCHFPGABANK35.ON<br>PSUSWITCHFPGABANK500/34.ON<br>PSUSWITCHFPGABANK501OUT||n.ON<br>DDRVREFREGULATORa.PGOOD||3<br>3<br>3<br>3<br>9||.3V||O||3.3V||Internally connected to DGND via 100K resistor

|J2.110||CB_PWR_GOOD ||1V0REGULATOR1.0VREGULATOR.ENABLE SOM_PGOOD_LOGIC.IN||n.a.||3.3VIN||I||3.3V||Internally connected to 3.3VIN via 10K resistor

|J2.112||SYS_RSTNSYS_RSTn||CPU.PS_SRST_B_501<br>MTR.~RST||B10<br>5C14||BANK 501||I||1.8V||Internally connected to 1.8V via 20K resistor

|J2.114||PORSTNPORSTn||CPU.PS_POR_B_500SV1.~RSTSV2.~RSTWD.~WDONOR.~RESET/RFU||C7B18557A4||BANK 500||I/O||3.3V||Internally connected to 3.3VIN via 2.2K resistorFor further details, please refer to [[Reset_scheme_(BoraXpress)#PORSTn_.28J2.114.29 | Reset_scheme_(BoraXpress)#PORSTn ]]

|J2.116||MRSTNMRSTn||MTRSV1.~MR||6||3.3VIN||I||3.3V||Internally connected to 3.3VIN via 2.2K resistorFor further details, please refer to [[Reset_scheme_(BoraXpress)#MRSTn_.28J2.116.29 |Reset_scheme_(BoraXpress)#MRSTn ]]

|J2.118||DGND||DGND||n.a.-||-||G||-||Digital ground

|J2.120||3.3VIN||+3.3 V3VIN||n.a.-||3.3VIN||S||+3.3V||SOM Power Supply

|J2.122||3.3VIN||+3.3 V3VIN||n.a.-||3.3VIN||S||+3.3V||SOM Power Supply

|J2.124||DGND||DGND||n.a.-||-||G||-||Digital ground

|J2.126||3.3VIN||+3.3 V3VIN||n.a.-||3.3VIN||S||+3.3V||SOM Power Supply

|J2.128||3.3VIN||+3.3 V3VIN||n.a.-||3.3VIN||S||+3.3V||SOM Power Supply

|J2.130||3.3VIN||+3.3 V3VIN||n.a.-||3.3VIN||S||+3.3V||SOM Power Supply

|J2.132||3.3VIN||+3.3 V3VIN||n.a.-||3.3VIN||S||+3.3V||SOM Power Supply

|J2.134||3.3VIN||+3.3 V3VIN||n.a.-||3.3VIN||S||+3.3V||SOM Power Supply

|J2.136||3.3VIN||+3.3 V3VIN||n.a.-||3.3VIN||S||+3.3V||SOM Power Supply

|J2.138||3.3VIN||+3.3 V3VIN||n.a.-||3.3VIN||S||+3.3V||SOM Power Supply

|J2.140||DGND||DGND||n.a.-||-||G||-||Digital ground