3,260
edits
Changes
m
→J3 odd pins (1 to 139)
|J3.93||DGND||DGND||n.a.||||||||
|-
|J3.95||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected anyway to an external I/O voltage as described in [[Programmable_logic_(Bora)]].
|-
|J3.97||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected anyway to an external I/O voltage as described in [[Programmable_logic_(Bora)]].
|-
|J3.99||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected anyway to an external I/O voltage as described in [[Programmable_logic_(Bora)]].
|-
|J3.101||DGND||DGND||n.a.||||||||
