3,260
edits
Changes
m
→J3 odd pins (1 to 139)
|J3.103||DGND||DGND||n.a.||||||||
|-
|J3.105||IO_L21P_T3_DQS_13||FPGA.IO_L21P_T3_DQS_13||V11||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.107||IO_L21N_T3_DQS_13||FPGA.IO_L21N_T3_DQS_13||V10||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.109||DGND||DGND||n.a.||||||||
|-
|J3.111||IO_L19P_T3_13||FPGA.IO_L19P_T3_13||T5||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.113||IO_L19N_T3_VREF_13||FPGA.IO_L19N_T3_VREF_13||U5||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.115||DGND||DGND||n.a.||||||||
|-
|J3.117||IO_L18P_T2_13||FPGA.IO_L18P_T2_13||W11||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.119||IO_L18N_T2_13||FPGA.IO_L18N_T2_13||Y11||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.121||DGND||DGND||n.a.||||||||
|-
|J3.123||IO_L16P_T2_13||FPGA.IO_L16P_T2_13||W10||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.125||IO_L16N_T2_13||FPGA.IO_L16N_T2_13||W9||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.127||DGND||DGND||n.a.||||||||
|-
|J3.129||IO_L14P_T2_SRCC_13||FPGA.IO_L14P_T2_SRCC_13||Y9||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.131||IO_L14N_T2_SRCC_13||FPGA.IO_L14N_T2_SRCC_13||Y8||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.133||DGND||DGND||n.a.||||||||
|-
|J3.135||IO_L12P_T1_MRCC_13||FPGA.IO_L12P_T1_MRCC_13||T9||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.137||IO_L12N_T1_MRCC_13||FPGA.IO_L12N_T1_MRCC_13||U10||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.139||DGND||DGND||n.a.||||||||
