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|J3.98||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must be connected anyway to an external I/O voltage as described in [[Programmable_logic_(Bora)]].
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|J3.100||IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||V5||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
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|J3.102||DGND||DGND||n.a.||||||||
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|J3.104||IO_L22P_T3_13||FPGA.IO_L22P_T3_13||V6||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
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|J3.106||IO_L22N_T3_13||FPGA.IO_L22N_T3_13||W6||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
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|J3.108||DGND||DGND||n.a.||||||||
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|J3.110||IO_L20P_T3_13||FPGA.IO_L20P_T3_13||Y12||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
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|J3.112||IO_L20N_T3_13||FPGA.IO_L20N_T3_13||Y13||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
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|J3.114||DGND||DGND||n.a.||||||||
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|J3.116||IO_L17P_T2_13||FPGA.IO_L17P_T2_13||U9||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
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|J3.118||IO_L17N_T2_13||FPGA.IO_L17N_T2_13||U8||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
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|J3.120||DGND||DGND||n.a.||||||||
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|J3.122||IO_L15P_T2_DQS_13||FPGA.IO_L15P_T2_DQS_13||V8||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
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|J3.124||IO_L15N_T2_DQS_13||FPGA.IO_L15N_T2_DQS_13||W8||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
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|J3.126||DGND||DGND||n.a.||||||||
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|J3.128||IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y7||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
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|J3.130||IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y6||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
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|J3.132||DGND||DGND||n.a.||||||||
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|J3.134||IO_L11P_T1_SRCC_13||FPGA.IO_L11P_T1_SRCC_13||U7||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
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|J3.136||IO_L11N_T1_SRCC_13||FPGA.IO_L11N_T1_SRCC_13||V7||||||||Not available on Bora SOMs equipped with the XC7Z010 SOC
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|J3.138||DGND||DGND||n.a.||||||||
