3,260
edits
Changes
m
→J2 even pins (2 to 140)
|J2.102||DGND||DGND||n.a.||||||||
|-
|J2.104||PS_MIO50_501||CPU.PS_MIO50_501<br>USBOTG.RESETB||B13<br>22||||||||For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(Bora)#PS_MIO50_501]]
|-
|J2.106||PS_MIO51_501||CPU.PS_MIO51_501<br>ETHPHY1GB.RESET_N||B9<br>42||||||||For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO51_501_.28J2.106.29 | Reset_scheme_(Bora)#PS_MIO51_501 ]]
|-
|J2.108||BOARD_PGOOD||PSUSWITCHFPGABANK13.ON<br>PSUSWITCHFPGABANK35.ON<br>PSUSWITCHFPGABANK500/34.ON<br>PSUSWITCHFPGABANK501.ON<br>DDRVREFREGULATOR.PGOOD||3<br>3<br>3<br>3<br>9||||||||
