Difference between revisions of "Pinout (Bora)"

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(Created page with "{{InfoBoxTop}} {{Applies To Bora}} {{InfoBoxBottom}} ==Introduction== This chapter contains the pinout description of the Bora module, grouped in six tables (two – odd and ...")
 
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** A = Analog signal
 
** A = Analog signal
 
* Voltage: I/O voltage levels
 
* Voltage: I/O voltage levels
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 +
==J1 odd pins (1 to 139)==
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{| class="wikitable" {| {{table}}
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| align="center" style="background:#f0f0f0;"|'''Pin'''
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| align="center" style="background:#f0f0f0;"|'''Pin Name'''
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| align="center" style="background:#f0f0f0;"|'''Internal Connections'''
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| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''
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| align="center" style="background:#f0f0f0;"|'''Supply Group'''
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| align="center" style="background:#f0f0f0;"|'''Type'''
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| align="center" style="background:#f0f0f0;"|'''Voltage'''
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| align="center" style="background:#f0f0f0;"|'''Note'''
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|-
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|-
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|J1.1||DGND||DGND||n.a.||||||||
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|-
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|J1.3||IO_L7P_T1_AD2P_35||FPGA.IO_L7P_T1_AD2P_35||M19||||||||
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|-
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|J1.5||IO_L10P_T1_AD11P_35||FPGA.IO_L10P_T1_AD11P_35||K19||||||||
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|-
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|J1.7||IO_L11P_T1_SRCC_35||FPGA.IO_L11P_T1_SRCC_35||L16||||||||
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|-
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|J1.9||IO_L8N_T1_AD10N_35||FPGA.IO_L8N_T1_AD10N_35||M18||||||||
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|-
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|J1.11||IO_L7N_T1_AD2N_35||FPGA.IO_L7N_T1_AD2N_35||M20||||||||
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|-
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|J1.13||DGND||DGND||n.a.||||||||
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|-
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|J1.15||IO_L9P_T1_DQS_AD3P_35||FPGA.IO_L9P_T1_DQS_AD3P_35||L19||||||||
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|-
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|J1.17||IO_L9N_T1_DQS_AD3N_35||FPGA.IO_L9N_T1_DQS_AD3N_35||L20||||||||
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|-
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|J1.19||DGND||DGND||n.a.||||||||
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|-
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|J1.21||IO_L20P_T3_AD6P_35||FPGA.IO_L20P_T3_AD6P_35||K14||||||||
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|-
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|J1.23||IO_L20N_T3_AD6N_35||FPGA.IO_L20N_T3_AD6N_35||J14||||||||
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|-
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|J1.25||IO_L22P_T3_AD7P_35||FPGA.IO_L22P_T3_AD7P_35||L14||||||||
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|-
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|J1.27||IO_L12N_T1_MRCC_35||FPGA.IO_L12N_T1_MRCC_35||K18||||||||
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|-
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|J1.29||DGND||DGND||n.a.||||||||
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|-
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|J1.31||IO_L21P_T3_DQS_AD14P_35||FPGA.IO_L21P_T3_DQS_AD14P_35||N15||||||||
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|-
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|J1.33||IO_L21N_T3_DQS_AD14N_35||FPGA.IO_L21N_T3_DQS_AD14N_35||N16||||||||
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|-
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|J1.35||DGND||DGND||n.a.||||||||
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|-
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|J1.37||IO_L17N_T2_AD5N_35||FPGA.IO_L17N_T2_AD5N_35||H20||||||||
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|-
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|J1.39||IO_L13N_T2_MRCC_35||FPGA.IO_L13N_T2_MRCC_35||H17||||||||
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|-
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|J1.41||IO_L19P_T3_35||FPGA.IO_L19P_T3_35||H15||||||||
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|-
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|J1.43||IO_L18P_T2_AD13P_35||FPGA.IO_L18P_T2_AD13P_35||G19||||||||
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|-
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|J1.45||IO_L16P_T2_35||FPGA.IO_L16P_T2_35||G17||||||||
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|-
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|J1.47||IO_L15N_T2_DQS_AD12N_35||FPGA.IO_L15N_T2_DQS_AD12N_35||F20||||||||
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|-
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|J1.49||DGND||DGND||n.a.||||||||
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|-
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|J1.51||IO_L2N_T0_AD8N_35||FPGA.IO_L2N_T0_AD8N_35||A20||||||||
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|-
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|J1.53||IO_L1N_T0_AD0N_35||FPGA.IO_L1N_T0_AD0N_35||B20||||||||
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|-
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|J1.55||IO_L5N_T0_AD9N_35||FPGA.IO_L5N_T0_AD9N_35||E19||||||||
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|-
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|J1.57||IO_L5P_T0_AD9P_35||FPGA.IO_L5P_T0_AD9P_35||E18||||||||
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|-
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|J1.59||DGND||DGND||n.a.||||||||
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|-
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|J1.61||IO_L3P_T0_DQS_AD1P_35||FPGA.IO_L3P_T0_DQS_AD1P_35||E17||||||||
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|-
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|J1.63||IO_L3N_T0_DQS_AD1N_35||FPGA.IO_L3N_T0_DQS_AD1N_35||D18||||||||
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|-
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|J1.65||DGND||DGND||n.a.||||||||
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|-
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|J1.67||VDDIO_BANK35||FPGA.VCCO_35||C19 - F18 - H14 - J17 - K20 - M16||||||||
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|-
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|J1.69||XADC_AGND||FPGA.GNDADC_0||J10||||||||
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|-
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|J1.71||XADC_AGND||FPGA.GNDADC_0||J10||||||||
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|-
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|J1.73||PS_MIO33_501||CPU.PS_MIO33_501||D15||||||||
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|-
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|J1.75||PS_MIO32_501||CPU.PS_MIO32_501||A14||||||||
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|-
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|J1.77||PS_MIO31_501||CPU.PS_MIO31_501||E16||||||||
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|-
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|J1.79||PS_MIO30_501||CPU.PS_MIO30_501||C15||||||||
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|-
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|J1.81||PS_MIO29_501||CPU.PS_MIO29_501||C13||||||||
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|-
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|J1.83||DGND||DGND||n.a.||||||||
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|-
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|J1.85||PS_MIO28_501||CPU.PS_MIO28_501||C16||||||||
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|-
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|J1.87||ETH_MDIO||CPU.PS_MIO53_501 - LAN.MDIO||C11 - 37||||||||
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|-
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|J1.89||ETH_MDC||CPU.PS_MIO12_501||C10||||||||
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|-
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|J1.91||ETH_LED1||LAN.LED1 / PME_N1||17||||||||
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|-
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|J1.93||ETH_LED2||LAN.LED2||15||||||||
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|-
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|J1.95||DGND||DGND||n.a.||||||||
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|-
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|J1.97||ETH_TXRX1_M||LAN.TXRXM_B||6||||||||
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|-
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|J1.99||ETH_TXRX1_P||LAN.TXRXP_B||5||||||||
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|-
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|J1.101||DGND||DGND||n.a.||||||||
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|-
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|J1.103||ETH_TXRX0_M||LAN.TXRXM_A||3||||||||
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|-
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|J1.105||ETH_TXRX0_P||LAN.TXRXP_A||2||||||||
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|-
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|J1.107||DVDDH||LAN.DVDDH||17 - 34 - 39||||||||
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|-
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|J1.109||N.C.||Not Connected||n.a.||||||||
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|-
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|J1.111||USBOTG_CPEN||USB.CPEN||7||||||||
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|-
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|J1.113||OTG_VBUS||USB.OTG_VBUS||2||||||||
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|-
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|J1.115||OTG_ID||USB.ID||1||||||||
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|-
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|J1.117||DGND||DGND||n.a.||||||||
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|-
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|J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500||A6||||||||
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|-
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|J1.121||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500||B7||||||||
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|-
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|J1.123||SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500||D6||||||||
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|-
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|J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500||B8||||||||
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|-
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|J1.127||DGND||DGND||n.a.||||||||
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|-
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|J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500||A5||||||||
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|-
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|J1.131||NAND_BUSY||CPU.PS_MIO14_500||C5||||||||
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|-
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|J1.133||PS_MIO15_500||CPU.PS_MIO15_500||C8||||||||
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|-
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|J1.135||N.C.||Not Connected||n.a.||||||||
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|-
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|J1.137||MEM_WPN||NAND.WP - NOR.WP/IO2||19 - C4||||||||
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|-
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|J1.139||DGND||DGND||n.a.||||||||
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|-
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|}
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==J1 even pins (2 to 140)==
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==J2 odd pins (1 to 139)==
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==J2 even pins (2 to 140)==
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==J3 odd pins (1 to 139)==
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==J3 even pins (2 to 140)==

Revision as of 14:31, 24 July 2013

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Info Box
Bora5-small.jpg Applies to Bora

Introduction[edit | edit source]

This chapter contains the pinout description of the Bora module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Bora connectors. Each row in the pinout tables contains the following information:

  • Pin: reference to the connector pin
  • Pin Name: pin (signal) name on the Bora connectors
  • Internal connections: connections to the Bora components
    • CPU.<x> : pin connected to CPU (processing system) pad named <x>
    • FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>
    • CAN.<x> : pin connected to the CAN transceiver
    • LAN.<x> : pin connected to the LAN PHY
    • USB.<x> : pin connected to the USB transceiver
    • NAND.<x>: pin connected to the flash NAND
    • NOR.<x>: pin connected to the flash NOR
    • SV.<x>: pin connected to voltage supervisor
    • MTR: pin connected to voltage monitors
  • Ball/pin #: Component ball/pin number connected to signal
  • Supply Group: Power Supply Group
  • Type: pin type
    • I = Input
    • O = Output
    • D = Differential
    • Z = High impedance
    • S = Power supply voltage
    • G = Ground
    • A = Analog signal
  • Voltage: I/O voltage levels

J1 odd pins (1 to 139)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Supply Group Type Voltage Note
J1.1 DGND DGND n.a.
J1.3 IO_L7P_T1_AD2P_35 FPGA.IO_L7P_T1_AD2P_35 M19
J1.5 IO_L10P_T1_AD11P_35 FPGA.IO_L10P_T1_AD11P_35 K19
J1.7 IO_L11P_T1_SRCC_35 FPGA.IO_L11P_T1_SRCC_35 L16
J1.9 IO_L8N_T1_AD10N_35 FPGA.IO_L8N_T1_AD10N_35 M18
J1.11 IO_L7N_T1_AD2N_35 FPGA.IO_L7N_T1_AD2N_35 M20
J1.13 DGND DGND n.a.
J1.15 IO_L9P_T1_DQS_AD3P_35 FPGA.IO_L9P_T1_DQS_AD3P_35 L19
J1.17 IO_L9N_T1_DQS_AD3N_35 FPGA.IO_L9N_T1_DQS_AD3N_35 L20
J1.19 DGND DGND n.a.
J1.21 IO_L20P_T3_AD6P_35 FPGA.IO_L20P_T3_AD6P_35 K14
J1.23 IO_L20N_T3_AD6N_35 FPGA.IO_L20N_T3_AD6N_35 J14
J1.25 IO_L22P_T3_AD7P_35 FPGA.IO_L22P_T3_AD7P_35 L14
J1.27 IO_L12N_T1_MRCC_35 FPGA.IO_L12N_T1_MRCC_35 K18
J1.29 DGND DGND n.a.
J1.31 IO_L21P_T3_DQS_AD14P_35 FPGA.IO_L21P_T3_DQS_AD14P_35 N15
J1.33 IO_L21N_T3_DQS_AD14N_35 FPGA.IO_L21N_T3_DQS_AD14N_35 N16
J1.35 DGND DGND n.a.
J1.37 IO_L17N_T2_AD5N_35 FPGA.IO_L17N_T2_AD5N_35 H20
J1.39 IO_L13N_T2_MRCC_35 FPGA.IO_L13N_T2_MRCC_35 H17
J1.41 IO_L19P_T3_35 FPGA.IO_L19P_T3_35 H15
J1.43 IO_L18P_T2_AD13P_35 FPGA.IO_L18P_T2_AD13P_35 G19
J1.45 IO_L16P_T2_35 FPGA.IO_L16P_T2_35 G17
J1.47 IO_L15N_T2_DQS_AD12N_35 FPGA.IO_L15N_T2_DQS_AD12N_35 F20
J1.49 DGND DGND n.a.
J1.51 IO_L2N_T0_AD8N_35 FPGA.IO_L2N_T0_AD8N_35 A20
J1.53 IO_L1N_T0_AD0N_35 FPGA.IO_L1N_T0_AD0N_35 B20
J1.55 IO_L5N_T0_AD9N_35 FPGA.IO_L5N_T0_AD9N_35 E19
J1.57 IO_L5P_T0_AD9P_35 FPGA.IO_L5P_T0_AD9P_35 E18
J1.59 DGND DGND n.a.
J1.61 IO_L3P_T0_DQS_AD1P_35 FPGA.IO_L3P_T0_DQS_AD1P_35 E17
J1.63 IO_L3N_T0_DQS_AD1N_35 FPGA.IO_L3N_T0_DQS_AD1N_35 D18
J1.65 DGND DGND n.a.
J1.67 VDDIO_BANK35 FPGA.VCCO_35 C19 - F18 - H14 - J17 - K20 - M16
J1.69 XADC_AGND FPGA.GNDADC_0 J10
J1.71 XADC_AGND FPGA.GNDADC_0 J10
J1.73 PS_MIO33_501 CPU.PS_MIO33_501 D15
J1.75 PS_MIO32_501 CPU.PS_MIO32_501 A14
J1.77 PS_MIO31_501 CPU.PS_MIO31_501 E16
J1.79 PS_MIO30_501 CPU.PS_MIO30_501 C15
J1.81 PS_MIO29_501 CPU.PS_MIO29_501 C13
J1.83 DGND DGND n.a.
J1.85 PS_MIO28_501 CPU.PS_MIO28_501 C16
J1.87 ETH_MDIO CPU.PS_MIO53_501 - LAN.MDIO C11 - 37
J1.89 ETH_MDC CPU.PS_MIO12_501 C10
J1.91 ETH_LED1 LAN.LED1 / PME_N1 17
J1.93 ETH_LED2 LAN.LED2 15
J1.95 DGND DGND n.a.
J1.97 ETH_TXRX1_M LAN.TXRXM_B 6
J1.99 ETH_TXRX1_P LAN.TXRXP_B 5
J1.101 DGND DGND n.a.
J1.103 ETH_TXRX0_M LAN.TXRXM_A 3
J1.105 ETH_TXRX0_P LAN.TXRXP_A 2
J1.107 DVDDH LAN.DVDDH 17 - 34 - 39
J1.109 N.C. Not Connected n.a.
J1.111 USBOTG_CPEN USB.CPEN 7
J1.113 OTG_VBUS USB.OTG_VBUS 2
J1.115 OTG_ID USB.ID 1
J1.117 DGND DGND n.a.
J1.119 SPI0_DQ3/MODE0/NAND_IO0 CPU.PS_MIO5_500 A6
J1.121 SPI0_DQ2/MODE2/NAND_IO2 CPU.PS_MIO4_500 B7
J1.123 SPI0_DQ1/MODE1/NAND_WE CPU.PS_MIO3_500 D6
J1.125 SPI0_DQ0/MODE3/NAND_ALE CPU.PS_MIO2_500 B8
J1.127 DGND DGND n.a.
J1.129 SPI0_SCLK/MODE4/NAND_IO1 CPU.PS_MIO6_500 A5
J1.131 NAND_BUSY CPU.PS_MIO14_500 C5
J1.133 PS_MIO15_500 CPU.PS_MIO15_500 C8
J1.135 N.C. Not Connected n.a.
J1.137 MEM_WPN NAND.WP - NOR.WP/IO2 19 - C4
J1.139 DGND DGND n.a.

J1 even pins (2 to 140)[edit | edit source]

J2 odd pins (1 to 139)[edit | edit source]

J2 even pins (2 to 140)[edit | edit source]

J3 odd pins (1 to 139)[edit | edit source]

J3 even pins (2 to 140)[edit | edit source]

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