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==Connectors and Pinout Table==
This chapter contains the pinout description of the Bora module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Bora connectors.
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA pinout specifications. See the images below for reference:
[[File:BORA_BOTTOM.png|700px|thumb|BORA BOTTOM view - J1, J2, J2 J3 connectors (pins 1-139, 2-140)|none]]
===Pinout table naming conventions ===
|J1.105||ETH_TXRX0_P||LAN.TXRXP_A||2||||D||3.3V||
|-
|J1.107||DVDDHD.N.C||LAN.DVDDH-|||16<br>34<br>40||||S||1.8V|Ethernet PHY VDDHDo Not Connect (reserved for internal use)
|-
|J1.109||N.C.||Not Connected||-||||||||
|J2.95||RTC_RST||RTC.~RST ||4||||I/O||3.3V||It can be left open if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
|-
|J2.97||XADC_VN_R||FPGA.VN_0||L10||||A / I||VREFP|See [[BELK-TN-012: Using XADC signal module|BELK-TN-012 Using XADC signal module]]
|-
|J2.99||XADC_VP_R||FPGA.VP_0||K9||||A / I||VREFP|See [[BELK-TN-012: Using XADC signal module|BELK-TN-012 Using XADC signal module]]
|-
|J2.101||N.C.||Not Connected||-||||||||
|-
|}
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