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===Pinout tablenaming conventions ===This chapter contains the pinout description of the Bora module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Bora connectors.
Each row in the pinout tables contains the following information:
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==SOM J1 odd ODD pins (1 to 139)declaration ==
{| class="wikitable" {| {{table}}
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|J1.91||ETH_LED1||LAN.LED1 / PME_N1||17||||I/O||1.8V||Internal 10K pull-up to DVDDH (i.e. PHYAD0 = 1) . Level translated translator needed if used @ 3V3
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|J1.93||ETH_LED2||LAN.LED2||15||||I/O||1.8V||Internal 10K pull-up to DVDDH (i.e. PHYAD1 = 1) . Level translated translator needed if used @ 3V3
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|J1.95||DGND||DGND||-||||G||||
|J1.105||ETH_TXRX0_P||LAN.TXRXP_A||2||||D||3.3V||
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|J1.107||DVDDHD.N.C||LAN.DVDDH-|||16<br>34<br>40||||S||1.8V|Ethernet PHY VDDHDo Not Connect (reserved for internal use)
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|J1.109||N.C.||Not Connected||-||||||||
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==SOM J1 even EVEN pins (2 to 140)declaration ==
{| class="wikitable" {| {{table}}
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==SOM J2 odd ODD pins (1 to 139)declaration ==
{| class="wikitable" {| {{table}}
|J2.95||RTC_RST||RTC.~RST ||4||||I/O||3.3V||It can be left open if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
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|J2.97||XADC_VN_R||FPGA.VN_0||L10||||A / I||VREFP|See [[BELK-TN-012: Using XADC signal module|BELK-TN-012 Using XADC signal module]]
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|J2.99||XADC_VP_R||FPGA.VP_0||K9||||A / I||VREFP|See [[BELK-TN-012: Using XADC signal module|BELK-TN-012 Using XADC signal module]]
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|J2.101||N.C.||Not Connected||-||||||||
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==SOM J2 even EVEN pins (2 to 140)declaration==
{| class="wikitable" {| {{table}}
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==SOM J3 odd ODD pins (1 to 139)declaration==
{| class="wikitable" {| {{table}}
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==SOM J3 even EVEN pins (2 to 140)declaration==
{| class="wikitable" {| {{table}}
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