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===Pinout tablenaming conventions ===This chapter contains the pinout description of the Bora module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Bora connectors.
Each row in the pinout tables contains the following information:
* CAN.<x> : pin connected to the CAN transceiver (TI SN65HVD232)
* LAN.<x> : pin connected to the LAN PHY (Microchip KSZ9031)
* USB.<x>: pin connected to the USB PHY (Microchip USB3317)
* NOR.<x>: pin connected to the NOR flash
* NAND.<x>: pin connected to the NAND flash
* G = Ground
* A = Analog signal
* A/G = Analog Ground
|-
|'''Notes'''
|}
==SOM J1 odd ODD pins (1 to 139)declaration ==
{| class="wikitable" {| {{table}}
|
|-
|J1.91||ETH_LED1||LAN.LED1 / PME_N1||17||||I/O||1.8V||level translated Internal 10K pull-up to DVDDH (i.e. PHYAD0 = 1) . Level translator needed if used @ 3V3
|-
|J1.93||ETH_LED2||LAN.LED2||15||||I/O||1.8V||level translated Internal 10K pull-up to DVDDH (i.e. PHYAD1 = 1) . Level translator needed if used @ 3V3
|-
|J1.95||DGND||DGND||-||||G||||
|J1.105||ETH_TXRX0_P||LAN.TXRXP_A||2||||D||3.3V||
|-
|J1.107||DVDDHD.N.C||LAN.DVDDH-|||16<br>34<br>40||||S||1.8V|Ethernet PHY VDDHDo Not Connect (reserved for internal use)
|-
|J1.109||N.C.||Not Connected||-||||||||
|-
|J1.111||USBOTG_CPEN||USB.CPEN||7||||O||1.8V||External 5V suply enable. For further details, please refer to the Microchip USB3317 datasheet.
|-
|J1.113||OTG_VBUS||USB.OTG_VBUS||2||||I/O||5V||USB VBUS comparator. For further details, please refer to the Microchip USB3317 datasheet.
|-
|J1.115||OTG_ID||USB.ID||1||||I||5V||ID of the USB cable. For further details, please refer to the Microchip USB3317 datasheet.
|-
|J1.117||DGND||DGND||-||||G||||
|}
==SOM J1 even EVEN pins (2 to 140)declaration ==
{| class="wikitable" {| {{table}}
|}
==SOM J2 odd ODD pins (1 to 139)declaration ==
{| class="wikitable" {| {{table}}
|J2.95||RTC_RST||RTC.~RST ||4||||I/O||3.3V||It can be left open if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
|-
|J2.97||XADC_VN_R||FPGA.VN_0||L10||||A / I||VREFP|See [[BELK-TN-012: Using XADC signal module|BELK-TN-012 Using XADC signal module]]
|-
|J2.99||XADC_VP_R||FPGA.VP_0||K9||||A / I||VREFP|See [[BELK-TN-012: Using XADC signal module|BELK-TN-012 Using XADC signal module]]
|-
|J2.101||N.C.||Not Connected||-||||||||
|J2.103||CONN_SPI_RSTn||NOR.~RESET/RFU ||A4||||||3.3V||
|-
|J2.105||CAN_L||CAN.L||6||||I/O||3.3V||For further details, please refer to the Texas Instruments SN65HVD232 datasheet.
|-
|J2.107||CAN_H||CAN.H||7||||I/O||3.3V||For further details, please refer to the Texas Instruments SN65HVD232 datasheet.
|-
|J2.109||DGND||DGND||-||||G||||
|}
==SOM J2 even EVEN pins (2 to 140)declaration==
{| class="wikitable" {| {{table}}
|J2.94||FPGA_DONE||FPGA.DONE_0||R11||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]
|-
|J2.96||WD_SET2||WDT.SET2||6||||I||3.3V||Internal 10K pull-up. For further details, please refer to the Maxim Integrated MAX6373 datasheet.
|-
|J2.98||WD_SET1||WDT.SET1||5||||I||3.3V||Internal 10K pull-up. For further details, please refer to the Maxim Integrated MAX6373 datasheet.
|-
|J2.100||WD_SET0||WDT.SET0||4||||I||3.3V||Internal 10K pull-down. For further details, please refer to the Maxim Integrated MAX6373 datasheet.
|-
|J2.102||DGND||DGND||-||||G||||
|J2.108||BOARD_PGOOD||PSUSWITCHFPGABANK13.ON<br>PSUSWITCHFPGABANK35.ON<br>PSUSWITCHFPGABANK500/34.ON<br>PSUSWITCHFPGABANK501.ON<br>DDRVREFREGULATOR.PGOOD||3<br>3<br>3<br>3<br>9||||O||3.3V||For further details, please refer to [[Power (Bora/BoraLite)|Power Supply (Bora)]]
|-
|J2.110||CB_PWR_GOOD ||1V0REGULATOR.ENABLE ||-||||I||3.3V||For further details, please refer to [[Power (Bora/BoraLite)|Power Supply (Bora)]]
|-
|J2.112||SYS_RSTN||CPU.PS_SRST_B_501<br>MTR.~RST||B10<br>5||||I||1.8V||For further details, please refer to [[Reset scheme (Bora/BoraLite)#Reset signals|Reset signals]]
|}
==SOM J3 odd ODD pins (1 to 139)declaration==
{| class="wikitable" {| {{table}}
|J3.91||N.C.||Not Connected||-||||||||
|-
|J3.93||DGND||DGND||-||||G||||
|-
|J3.95||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|J3.97||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|J3.99||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|J3.101||DGND||DGND||-||||G||||
|-
|J3.103||DGND||DGND||-||||G||||
|-
|J3.105||IO_L21P_T3_DQS_13||FPGA.IO_L21P_T3_DQS_13||V11||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.107||IO_L21N_T3_DQS_13||FPGA.IO_L21N_T3_DQS_13||V10||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.109||DGND||DGND||-||||G||||
|-
|J3.111||IO_L19P_T3_13||FPGA.IO_L19P_T3_13||T5||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.113||IO_L19N_T3_VREF_13||FPGA.IO_L19N_T3_VREF_13||U5||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.115||DGND||DGND||-||||G||||
|-
|J3.117||IO_L18P_T2_13||FPGA.IO_L18P_T2_13||W11||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.119||IO_L18N_T2_13||FPGA.IO_L18N_T2_13||Y11||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.121||DGND||DGND||-||||G||||
|-
|J3.123||IO_L16P_T2_13||FPGA.IO_L16P_T2_13||W10||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.125||IO_L16N_T2_13||FPGA.IO_L16N_T2_13||W9||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.127||DGND||DGND||-||||G||||
|-
|J3.129||IO_L14P_T2_SRCC_13||FPGA.IO_L14P_T2_SRCC_13||Y9||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.131||IO_L14N_T2_SRCC_13||FPGA.IO_L14N_T2_SRCC_13||Y8||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.133||DGND||DGND||-||||G||||
|-
|J3.135||IO_L12P_T1_MRCC_13||FPGA.IO_L12P_T1_MRCC_13||T9||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.137||IO_L12N_T1_MRCC_13||FPGA.IO_L12N_T1_MRCC_13||U10||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.139||DGND||DGND||-||||G||||
|-
|}
==SOM J3 even EVEN pins (2 to 140)declaration==
{| class="wikitable" {| {{table}}
|J3.66||N.C.||Not Connected||-||||||||
|-
|J3.68||DGND||DGND||-||||G||||
|-
|J3.70||N.C.||Not Connected||-||||||||
|J3.92||MON_1.0V||n.a.||-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|J3.94||DGND||DGND||-||||G||||
|-
|J3.96||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|J3.98||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|J3.100||IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||V5||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.102||DGND||DGND||-||||G||||
|-
|J3.104||IO_L22P_T3_13||FPGA.IO_L22P_T3_13||V6||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.106||IO_L22N_T3_13||FPGA.IO_L22N_T3_13||W6||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.108||DGND||DGND||-||||G||||
|-
|J3.110||IO_L20P_T3_13||FPGA.IO_L20P_T3_13||Y12||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.112||IO_L20N_T3_13||FPGA.IO_L20N_T3_13||Y13||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.114||DGND||DGND||-||||G||||
|-
|J3.116||IO_L17P_T2_13||FPGA.IO_L17P_T2_13||U9||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.118||IO_L17N_T2_13||FPGA.IO_L17N_T2_13||U8||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.120||DGND||DGND||-||||G||||
|-
|J3.122||IO_L15P_T2_DQS_13||FPGA.IO_L15P_T2_DQS_13||V8||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.124||IO_L15N_T2_DQS_13||FPGA.IO_L15N_T2_DQS_13||W8||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.126||DGND||DGND||-||||G||||
|-
|J3.128||IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y7||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.130||IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y6||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.132||DGND||DGND||-||||G||||
|-
|J3.134||IO_L11P_T1_SRCC_13||FPGA.IO_L11P_T1_SRCC_13||U7||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.136||IO_L11N_T1_SRCC_13||FPGA.IO_L11N_T1_SRCC_13||V7||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.138||DGND||DGND||-||||G||||
|-
|J3.140||DGND||DGND||-||||G||||
|-
|}
<section end="Body" />
