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<section begin=History/>{| style="border-collapse:collapse; "!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History|- !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:whiteBody"|Version!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|X.Y.Z|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD|-|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|[TBD_link X.Y.Z]|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|-|}<section end=History/><section begin=Body/>''TBD: modificare la tabella seguente con le caratteristiche dei pin del SOM'' ''TBD: modificare le due tabelle ODD e EVEN con la mappa completa dei pins'' '''TBD: nella tabella naming conventions, inserire il codice dei vari IC presenti (PMIC, PHY ETH, ecc.)'''
==Connectors and Pinout Table==
This chapter contains the pinout description of the Bora module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Bora connectors.
=== Connectors description ===
In the following table are described all available the interface connectors integrated on [[BORA:Category:Bora | Bora]]SOM:
{| class="wikitable"
|-
!Carrier board counterpart
|-
|J1, J2, J3|SODIMM DDR3 edge connector 204 pinHirose FX8C-140S-SV<br>3x140 pins 0.6mm pitch connectors
|
|TE Connectivity 2Hirose FX8C-2013289140P-1SV''<x>''where ''<x''> stays for:|* ''empty'' = 5 mm board-to-board height|Jxx* 1 = 6 mm board-to-board height|TBD* 2 = 7 mm board-to-board height|TBD|TBD|* 4 = 9 mm board-to-board height|Jxx|TBD|TBD|TBD|* 6 = 11 mm board-|Jxx|TBD|TBD|TBD|to-|Jxx|TBD|TBD|TBDboard height
|}
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA pinout specifications. See the images below for reference:
[[File:BORA-topBORA_BOTTOM.png|500px700px|thumb|BORA TOP BOTTOM view|none]][[File:BORA-bottom.png|500px|thumb|BORA BOTTOM viewJ1, J2, J3 connectors (pins 1-139, 2-140)|none]]
===Pinout table naming conventions ===
Each row in the pinout tables contains the following information:
{|class="wikitable" style="width:50%;"
|-
|'''Pin'''
|-
|'''Pin Name'''
| Pin (signal) name on the BORA AxelLite connectors
|-
|'''Internal<br>connections'''
| Connections to the BORA components
* CPU.<x> : pin connected to CPU pad named <x>
* CAN.<x> : pin connected to the CAN transceiver (''manufacturer'' ''part number''TI SN65HVD232)* PMICLAN.<x> : pin connected to the Power Manager IC LAN PHY (''manufacturer'' ''part number''Microchip KSZ9031)* LANUSB.<x> : pin connected to the LAN USB PHY (''manufacturer'' ''part number''Microchip USB3317)* NOR.<x>: pin connected to the NOR flash NOR* SVNAND.<x>: pin connected to voltage supervisorthe NAND flash* IO_L<x>: pin connected to PL (FPGA)
* MTR: pin connected to voltage monitors
* MON_<x>: pin for external voltage monitoring
|-
|'''Ball/pin #'''
| Component ball/pin number connected to signal
|-
|'''Voltage''' || I/O voltage levels * 1.8V* 3.3V* U.D. = User Defined
|-
|'''Type'''
* G = Ground
* A = Analog signal
* A/G = Analog Ground
|-
|'''Notes'''
|Remarks on special pin characteristics
|-
|}
==Pinout Table SOM J1 ODD pins (1 to 139) declaration ==
{| class="wikitable" {| {{table}}! latexfontsize| style="background:#f0f0f0;" align="scriptsizecenter"| '''Pin '''! latexfontsize| style="background:#f0f0f0;" align="scriptsizecenter"| '''Pin Name'''! latexfontsize| style="background:#f0f0f0;" align="scriptsizecenter"| '''Internal Connections '''! latexfontsize| style="background:#f0f0f0;" align="scriptsizecenter"| '''Ball/pin # '''! latexfontsize| style="background:#f0f0f0;" align="scriptsizecenter"| Voltage domain'''Supply Group'''! latexfontsize| style="background:#f0f0f0;" align="scriptsizecenter"| '''Type '''! latexfontsize| style="background:#f0f0f0;" align="scriptsizecenter"| Notes'''Voltage'''! colspan| style="2background:#f0f0f0;" latexfontsizealign="scriptsizecenter"| Alternative Functions'''Note'''
|-
|-
|Pin ALT-1J1.3||IO_L7P_T1_AD2P_35||FPGA.IO_L7P_T1_AD2P_35||M19||BANK35|I/O|ECSPI5_MOSIU.D.||
|-
|Pin ALT-2J1.5||IO_L10P_T1_AD11P_35||FPGA.IO_L10P_T1_AD11P_35||K19||BANK35|I/O|KEY_ROW5U.D.||
|-
|Pin ALT-3J1.7||IO_L11P_T1_SRCC_35||FPGA.IO_L11P_T1_SRCC_35||L16||BANK35|I/O|AUD4_RXCU.D.||
|-
|Pin ALT-5J1.9||IO_L8N_T1_AD10N_35||FPGA.IO_L8N_T1_AD10N_35||M18||BANK35|I/O|GPIO1_IO11U.D.||
|-
|-
|Pin ALTJ1.13||DGND||DGND||-1|TBD|||G||||
|-
|Pin ALT-2J1.15||IO_L9P_T1_DQS_AD3P_35||FPGA.IO_L9P_T1_DQS_AD3P_35||L19||BANK35|I/O|TBDU.D.||
|-
|Pin ALT-3J1.17||IO_L9N_T1_DQS_AD3N_35||FPGA.IO_L9N_T1_DQS_AD3N_35||L20||BANK35|I/O|TBDU.D.||
|-
|Pin ALTJ1.19||DGND||DGND||-5|TBD|||G||||
|-
|-
|Pin ALT-1J1.23||IO_L20N_T3_AD6N_35||FPGA.IO_L20N_T3_AD6N_35||J14||BANK35|I/O|TBDU.D.||
|-
|Pin ALT-2J1.25||IO_L22P_T3_AD7P_35||FPGA.IO_L22P_T3_AD7P_35||L14||BANK35|I/O|TBDU.D.||
|-
|Pin ALT-3J1.27||IO_L12N_T1_MRCC_35||FPGA.IO_L12N_T1_MRCC_35||K18||BANK35|I/O|TBDU.D.||
|-
|Pin ALTJ1.29||DGND||DGND||-5|TBD|||G||||
|-
|-
|Pin ALT-1J1.33||IO_L21N_T3_DQS_AD14N_35||FPGA.IO_L21N_T3_DQS_AD14N_35||N16||BANK35|I/O|TBDU.D.||
|-
|Pin ALTJ1.35||DGND||DGND||-2|TBD|||G||||
|-
|Pin ALT-3J1.37||IO_L17N_T2_AD5N_35||FPGA.IO_L17N_T2_AD5N_35||H20||BANK35|I/O|TBDU.D.||
|-
|Pin ALT-5J1.39||IO_L13N_T2_MRCC_35||FPGA.IO_L13N_T2_MRCC_35||H17||BANK35|I/O|TBDU.D.||
|-
|-
|Pin ALT-1J1.43||IO_L18P_T2_AD13P_35||FPGA.IO_L18P_T2_AD13P_35||G19||BANK35|I/O|TBDU.D.||
|-
|Pin ALT-2J1.45||IO_L16P_T2_35||FPGA.IO_L16P_T2_35||G17||BANK35|I/O|TBD||
|-
|Pin ALT-3J1.47||IO_L15N_T2_DQS_AD12N_35||FPGA.IO_L15N_T2_DQS_AD12N_35||F20||BANK35|I/O|TBDU.D.||
|-
|Pin ALTJ1.49||DGND||DGND||-5|TBD|||G||||
|-
|-
|Pin ALT-1J1.53||IO_L1N_T0_AD0N_35||FPGA.IO_L1N_T0_AD0N_35||B20||BANK35|I/O|TBDU.D.||
|-
|Pin ALT-2J1.55||IO_L5N_T0_AD9N_35||FPGA.IO_L5N_T0_AD9N_35||E19||BANK35|I/O|TBDU.D.||
|-
|Pin ALT-3J1.57||IO_L5P_T0_AD9P_35||FPGA.IO_L5P_T0_AD9P_35||E18||BANK35|I/O|TBDU.D.||
|-
|Pin ALTJ1.59||DGND||DGND||-5|TBD|||G||||
|-
|-
|Pin ALT-1J1.63||IO_L3N_T0_DQS_AD1N_35||FPGA.IO_L3N_T0_DQS_AD1N_35||D18||BANK35|I/O|TBDU.D.||
|-
|Pin ALTJ1.65||DGND||DGND||-2|TBD|||G||||
|-
|Pin ALT-J1.67||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||BANK35|S||||User Defined: 1.8V to 3.3V (see [[Programmable logic (Bora)#Introduction|TBDProgrammable logic (Bora)]] )
|-
|Pin ALT-5J1.69||XADC_AGND||FPGA.GNDADC_0||J10||||A / G||||TBD
|-
|-
|Pin ALT-J1.73||PS_MIO45_501 ||CPU.PS_MIO45_501||B15||BANK501|I/O|1.8V|TBD
|-
|Pin ALT-2J1.75||PS_MIO44_501||CPU.PS_MIO44_501||F13||BANK501|I/O|1.8V|TBD
|-
|Pin ALT-3J1.77||PS_MIO43_501||CPU.PS_MIO43_501||A9||BANK501|I/O|1.8V|TBD
|-
|Pin ALT-5J1.79||PS_MIO42_501||CPU.PS_MIO42_501||E12||BANK501|I/O|1.8V|TBD
|-
|-
|Pin ALTJ1.83||DGND||DGND||-1|TBD|||G||||
|-
|Pin ALT-2J1.85||PS_MIO40_501||CPU.PS_MIO40_501||D14||BANK501|I/O|1.8V|TBD
|-
|Pin ALT-3J1.87||ETH_MDIO||CPU.PS_MIO53_501<br>LAN.MDIO||C11<br>37||BANK501|I/O|1.8V|TBD
|-
|Pin ALT-5J1.89||ETH_MDC||CPU.PS_MIO12_501<br>LAN.MDC||C10<br>36||BANK501|I/O|1.8V|TBD
|-
|-
|Pin ALTJ1.93||ETH_LED2||LAN.LED2||15||||I/O||1.8V||Internal 10K pull-up to DVDDH (i.e. PHYAD1 = 1|TBD) . Level translator needed if used @ 3V3
|-
|Pin ALTJ1.95||DGND||DGND||-2|TBD|||G||||
|-
|Pin ALT-J1.97||ETH_TXRX1_M||LAN.TXRXM_B||6||||D||3.3V||TBD
|-
|Pin ALT-J1.99||ETH_TXRX1_P||LAN.TXRXP_B||5|TBD|||D||3.3V||
|-
|-
|Pin ALT-1J1.103||ETH_TXRX0_M||LAN.TXRXM_A||3||||D||3.3V||TBD
|-
|Pin ALT-J1.105||ETH_TXRX0_P||LAN.TXRXP_A||2|TBD|||D||3.3V||
|-
|Pin ALTJ1.107||D.N.C||-3|TBD||||||| ||Do Not Connect (reserved for internal use)
|-
|Pin ALTJ1.109||N.C.||Not Connected||-5|TBD|||||||
|-
|-
|Pin ALT-1J1.113|TBD|OTG_VBUS||USB.OTG_VBUS||2||||I/O||5V||USB VBUS comparator. For further details, please refer to the Microchip USB3317 datasheet.
|-
|Pin ALT-2J1.115|TBD|OTG_ID||USB.ID||1||||I||5V||ID of the USB cable. For further details, please refer to the Microchip USB3317 datasheet.
|-
|Pin ALTJ1.117||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-5J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500||A6||BANK500|I/O||3.3V|TBDInternally connected as NAND I/O (if populated)This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|-
|Pin ALT-1J1.123||SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500||D6||BANK500|I/O||3.3V|TBDInternally connected as NAND I/O (if populated)This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|Pin ALT-2J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500||B8||BANK500|I/O||3.3V|TBDInternally connected as NAND I/O (if populated)This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|Pin ALTJ1.127||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-5J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500||A5||BANK500|I/O||3.3V|TBDInternally connected as NAND I/O (if populated)This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|-
|Pin ALT-J1.133||PS_MIO15_500||CPU.PS_MIO15_500<br>WDT.WDI||C8<br>1||BANK500|I/O||3.3V|TBDSee also [[Watchdog_(Bora)|this page]]
|-
|Pin ALTJ1.135||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ1.137||MEM_WPN||NAND.WP - NOR.WP/IO2||19 -3C4||||I/O||||TBDInternally connected to NAND and NOR WP
|-
|Pin ALTJ1.139||DGND||DGND||-5|TBD|||G||||
|-
|rowspan} ==SOM J1 EVEN pins (2 to 140) declaration == {| class="5wikitable"{|J1.29{{table}}|rowspanstyle="5background:#f0f0f0;" align="center"|TBD'''Pin'''|rowspanstyle="5background:#f0f0f0;" align="center"|TBD'''Pin Name'''|rowspanstyle="5background:#f0f0f0;" align="center"|TBD'''Internal Connections'''|rowspanstyle="background:#f0f0f0;" align="5center"|TBD'''Ball/pin #'''|rowspanstyle="background:#f0f0f0;" align="5center"|TBD'''Supply Group'''|rowspanstyle="background:#f0f0f0;" align="5center"|TBD'''Type'''|Pin ALT-0style="background:#f0f0f0;" align="center" |'''Voltage'''|TBDstyle="background:#f0f0f0;" align="center" |'''Note'''
|-
|Pin ALT-J1.2||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||BANK35|S||||User Defined: 1.8V to 3.3V (see [[Programmable logic (Bora)#Introduction|TBDProgrammable logic (Bora)]] )
|-
|Pin ALTJ1.4||DGND||DGND||-2|TBD|||G||||
|-
|Pin ALT-3J1.6||IO_L10N_T1_AD11N_35||FPGA.IO_L10N_T1_AD11N_35||J19||BANK35|TBDI/O||U.D.||
|-
|Pin ALT-5J1.8||IO_L12P_T1_MRCC_35||FPGA.IO_L12P_T1_MRCC_35||K17||BANK35|TBDI/O||U.D.||
|-
|-
|Pin ALT-1J1.12||IO_L8P_T1_AD10P_35||FPGA.IO_L8P_T1_AD10P_35||M17||BANK35|TBDI/O||U.D.||
|-
|Pin ALTJ1.14||DGND||DGND||-2|TBD|||G||||
|-
|Pin ALT-3J1.16||IO_L24N_T3_AD15N_35||FPGA.IO_L24N_T3_AD15N_35||J16||BANK35|TBDI/O||U.D.||
|-
|Pin ALT-5J1.18||IO_25_35||FPGA.IO_25_35||J15||BANK35|TBDI/O||U.D.||
|-
|-
|Pin ALT-1J1.22||IO_L23N_T3_35||FPGA.IO_L23N_T3_35||M15||BANK35|TBDI/O||U.D.||
|-
|Pin ALTJ1.24||DGND||DGND||-2|TBD|||G||||
|-
|Pin ALT-3J1.26||IO_L22N_T3_AD7N_35||FPGA.IO_L22N_T3_AD7N_35||L15||BANK35|TBDI/O||U.D.||
|-
|Pin ALT-5J1.28||IO_L23P_T3_35||FPGA.IO_L23P_T3_35||M14||BANK35|TBDI/O||U.D.||
|-
|-
|Pin ALT-1J1.32||IO_L17P_T2_AD5P_35||FPGA.IO_L17P_T2_AD5P_35||J20||BANK35|TBDI/O||U.D.||
|-
|Pin ALT-2J1.34||IO_L14P_T2_AD4P_SRCC_35||FPGA.IO_L14P_T2_AD4P_SRCC_35||J18||BANK35|TBDI/O||U.D.||
|-
|Pin ALT-3J1.36||IO_L14N_T2_AD4N_SRCC_35||FPGA.IO_L14N_T2_AD4N_SRCC_35||H18||BANK35|TBDI/O||U.D.||
|-
|Pin ALTJ1.38||DGND||DGND||-5|TBD|||G||||
|-
|-
|Pin ALT-1J1.42||IO_L18N_T2_AD13N_35||FPGA.IO_L18N_T2_AD13N_35||G20||BANK35|TBDI/O||U.D.||
|-
|Pin ALT-2J1.44||IO_L16N_T2_35||FPGA.IO_L16N_T2_35||G18||BANK35|TBDI/O||U.D.||
|-
|Pin ALT-3J1.46||IO_L15P_T2_DQS_AD12P_35||FPGA.IO_L15P_T2_DQS_AD12P_35||F19||BANK35|TBDI/O||U.D.||
|-
|Pin ALTJ1.48||DGND||DGND||-5|TBD|||G||||
|-
|-
|Pin ALT-1J1.52||IO_L2P_T0_AD8P_35||FPGA.IO_L2P_T0_AD8P_35||B19||BANK35|TBDI/O||U.D.||
|-
|Pin ALT-2J1.54||IO_L4N_T0_35||FPGA.IO_L4N_T0_35||D20||BANK35|TBDI/O||U.D.||
|-
|Pin ALT-3J1.56||IO_L4P_T0_35||FPGA.IO_L4P_T0_35||D19||BANK35|TBDI/O||U.D.||
|-
|Pin ALT-5J1.58||IO_L6P_T0_35||FPGA.IO_L6P_T0_35||F16||BANK35|TBDI/O||U.D.||
|-
|-
|Pin ALT-1J1.62||IO_L6N_T0_VREF_35||FPGA.IO_L6N_T0_VREF_35||F17||BANK35|TBDI/O||U.D.||
|-
|Pin ALT-2J1.64||IO_L19N_T3_VREF_35||FPGA.IO_L19N_T3_VREF_35||G15||BANK35|TBDI/O||U.D.||
|-
|Pin ALT-J1.66||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||BANK35|S||||User Defined: 1.8V to 3.3V (see [[Programmable logic (Bora)#Introduction|TBDProgrammable logic (Bora)]] )
|-
|Pin ALT-5J1.68||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||BANK35|TBDS||||User Defined: 1.8V to 3.3V (see [[Programmable logic (Bora)#Introduction|Programmable logic (Bora)]] )
|-
|-
|Pin ALT-1J1.72||XADC_AGND||FPGA.GNDADC_0||J10||||A/G||||TBD
|-
|Pin ALT-2J1.74||IO_0_35||FPGA.IO_0_35||G14||BANK35||I/O||U.D.||TBD
|-
|Pin ALTJ1.76||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ1.78||N.C.||Not Connected||-5|TBD|||||||
|-
|-
|Pin ALT-J1.82||PS_MIO48_501||CPU.PS_MIO48_501||B12||BANK501||I/O||1.8V||TBDConfigured as UART1_TX on BELK BSP
|-
|Pin ALTJ1.84||PS_MIO47_501||CPU.PS_MIO47_501||B14||BANK501||I/O||1.8V||Internally connected as I2C0_SDA (10K pull-2|TBDup)
|-
|Pin ALTJ1.86||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALTJ1.88||PS_MIO46_501||CPU.PS_MIO46_501||D16||BANK501||I/O||1.8V||Internally connected as I2C0_CLK (10K pull-5|TBDup)
|-
|-
|Pin ALTJ1.92||DGND||DGND||-1|TBD|||G||||
|-
|Pin ALT-2J1.94||ETH_TXRX3_M||LAN.TXRXM_D||11||||D||3.3V||TBD
|-
|Pin ALT-J1.96||ETH_TXRX3_P||LAN.TXRXP_D||10||||D||3.3V||TBD
|-
|Pin ALTJ1.98||DGND||DGND||-5|TBD|||G||||
|-
|-
|Pin ALT-1J1.102||ETH_TXRX2_P||LAN.TXRXP_C||7||||D||3.3V||TBD
|-
|Pin ALTJ1.104||DGND||DGND||-2|TBD|||G||||
|-
|Pin ALT-3J1.106||CLK125_NDO||LAN.CLK125_NDO||41||||I/O||1.8V||TBD
|-
|Pin ALTJ1.108||N.C.||Not Connected||-5|TBD|||||||
|-
|-
|Pin ALTJ1.112||DGND||DGND||-1|TBD|||G||||
|-
|Pin ALT-2J1.114||USBP1||USB.DP||6||||D||||TBD
|-
|Pin ALT-3J1.116||USBM1||USB.DM||5||||D||||TBD
|-
|Pin ALTJ1.118||DGND||DGND||-5|TBD|||G||||
|-
|-
|Pin ALT-1J1.122||NAND_CS0/SPI0_CS1||CPU.PS_MIO0_500<br>NAND.~CE||E6<br>9||BANK500|I/O||3.3V|TBDInternally connected as NAND chip select (if populated)
|-
|Pin ALT-2J1.124||NAND_IO3||CPU.PS_MIO13_500<br>NAND.I/O3||E8<br>32||BANK500|I/O||3.3V|TBDInternally connected as NAND I/O (if populated)
|-
|Pin ALT-J1.126||NAND_IO4||CPU.PS_MIO9_500<br>NAND.I/O4||B5<br>41||BANK500|I/O||3.3V|TBDInternally connected as NAND I/O (if populated)
|-
|Pin ALT-5J1.128||NAND_IO5||CPU.PS_MIO10_500<br>NAND.I/O5||E9<br>42||BANK500|I/O||3.3V|TBDInternally connected as NAND I/O (if populated)
|-
|-
|Pin ALT-1J1.132||NAND_IO6||CPU.PS_MIO11_500<br>NAND.I/O6||C6<br>43||BANK500|I/O||3.3V|TBDInternally connected as NAND I/O (if populated)
|-
|Pin ALT-2J1.134||NAND_IO7||CPU.PS_MIO12_500<br>NAND.I/O7||D9<br>44||BANK500|I/O||3.3V|TBDInternally connected as NAND I/O (if populated)
|-
|Pin ALT-J1.136||NAND_RD_B/VCFG1||CPU.PS_MIO8_500<br>NAND.~RE||D5<br>8||BANK500|I/O||3.3V|TBDThis signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|Pin ALT-5J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500<br>NAND.CLE||D8<br>16||BANK500|I/O||3.3V|TBDThis signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|-
|} ==SOM J2 ODD pins (1 to 139) declaration == {| class="wikitable" {| {{table}}| style="background:#f0f0f0;" align="center" |'''Pin'''| style="background:#f0f0f0;" align="center" |'''Pin ALT-1Name'''| style="background:#f0f0f0;" align="center" |'''Internal Connections'''| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''| style="background:#f0f0f0;" align="center" |'''Supply Group'''| style="background:#f0f0f0;" align="center" |'''Type'''| style="background:#f0f0f0;" align="center" |'''Voltage'''|TBDstyle="background:#f0f0f0;" align="center" |'''Note'''
|-
|Pin ALTJ2.1||DGND||DGND||-2|TBD|||G||||
|-
|Pin ALTJ2.3||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-J2.5|TBD|IO_L8P_T1_34||FPGA.IO_L8P_T1_34||W14||BANK34||I/O||3.3V||
|-
|rowspan="5"|J1J2.497|rowspan="5"|TBDIO_L8N_T1_34|rowspan="5"|TBDFPGA.IO_L8N_T1_34|rowspan="5"|TBDY14|rowspan="5"|TBDBANK34|rowspan="5"|TBDI/O|rowspan="5"|TBD3.3V|Pin ALT-0|TBD
|-
|Pin ALT-J2.9||IO_L6P_T0_34||CAN.D<br>FPGA.IO_L6P_T0_34||1<br>P14||BANK34||I/O||3.3V||TBDBy default used as CAN.TX with internal CAN PHY transceiver (mount option)
|-
|Pin ALT-2J2.11||IO_L6N_T0_VREF_34||FPGA.IO_L6N_T0_VREF_34||R14||BANK34||I/O||3.3V||TBD
|-
|Pin ALTJ2.13||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALTJ2.15||IO_L3P_T0_DQS_PUDC_B_34||FPGA.IO_L3P_T0_DQS_PUDC_B_34||U13||BANK34||I/O||3.3V||Internal 10K resistor pull-5|TBDup
|-
|rowspan="5"|J1J2.5117|rowspan="5"|TBDIO_L3N_T0_DQS_34|rowspan="5"|TBDFPGA.IO_L3N_T0_DQS_34|rowspan="5"|TBDV13|rowspan="5"|TBDBANK34|rowspan="5"|TBDI/O|rowspan="5"|TBD3.3V|Pin ALT-0|TBD
|-
|Pin ALT-1J2.19||IO_L2P_T0_34||FPGA.IO_L2P_T0_34||T12||BANK34||I/O||3.3V||TBD
|-
|Pin ALT-2J2.21||IO_L2N_T0_34||FPGA.IO_L2N_T0_34||U12||BANK34||I/O||3.3V||TBD
|-
|Pin ALTJ2.23||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-5J2.25||IO_L22P_T3_34||FPGA.IO_L22P_T3_34||W18||BANK34||I/O||3.3V||TBD
|-
|rowspan="5"|J1J2.5327|rowspan="5"|TBDIO_L22N_T3_34|rowspan="5"|TBDFPGA.IO_L22N_T3_34|rowspan="5"|TBDW19|rowspan="5"|TBDBANK34|rowspan="5"|TBDI/O|rowspan="5"|TBD3.3V|Pin ALT-0|TBD
|-
|Pin ALT-1J2.29||IO_L21P_T3_DQS_34||FPGA.IO_L21P_T3_DQS_34||V17||BANK34||I/O||3.3V||TBD
|-
|Pin ALT-2J2.31||IO_L21N_T3_DQS_34||FPGA.IO_L21N_T3_DQS_34||V18||BANK34||I/O||3.3V||TBD
|-
|Pin ALTJ2.33||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-5J2.35|TBD|IO_L19P_T3_34||CAN.R<br>FPGA.IO_L19P_T3_34||4<br>R16||BANK34||I/O||3.3V||By default used as CAN.RX with internal CAN PHY transceiver (mount option)
|-
|rowspan="5"|J1J2.5537|rowspan="5"|TBDIO_L19N_T3_VREF_34|rowspan="5"|TBDFPGA.IO_L19N_T3_VREF_34|rowspan="5"|TBDR17|rowspan="5"|TBDBANK34|rowspan="5"|TBDI/O|rowspan="5"|TBD3.3V|Pin ALT-0|TBD
|-
|Pin ALT-1J2.39||IO_L18P_T2_34||FPGA.IO_L18P_T2_34||V16||BANK34||I/O||3.3V||TBD
|-
|Pin ALT-2J2.41||IO_L18N_T2_34||FPGA.IO_L18N_T2_34||W16||BANK34||I/O||3.3V||TBD
|-
|Pin ALTJ2.43||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-5J2.45||IO_L15P_T2_DQS_34||FPGA.IO_L15P_T2_DQS_34||T20||BANK34||I/O||3.3V||TBD
|-
|rowspan="5"|J1J2.5747|rowspan="5"|TBDIO_L15N_T2_DQS_34|rowspan="5"|TBDFPGA.IO_L15N_T2_DQS_34|rowspan="5"|TBDU20|rowspan="5"|TBDBANK34|rowspan="5"|TBDI/O|rowspan="5"|TBD3.3V|Pin ALT-0|TBD
|-
|Pin ALTJ2.49||DGND||DGND||-1|TBD|||||||
|-
|Pin ALT-2J2.51||IO_L13P_T1_MRCC_34||FPGA.IO_L13P_T1_MRCC_34||N18||BANK34||I/O||3.3V||TBD
|-
|Pin ALT-J2.53||IO_L13N_T1_MRCC_34||FPGA.IO_L13N_T1_MRCC_34||P19||BANK34||I/O||3.3V||TBD
|-
|Pin ALTJ2.55||DGND||DGND||-5|TBD|||||||
|-
|rowspan="5"|J1J2.5957|rowspan="5"|TBDIO_L11P_T1_SRCC_34|rowspan="5"|TBDFPGA.IO_L11P_T1_SRCC_34|rowspan="5"|TBDU14|rowspan="5"|TBDBANK34|rowspan="5"|TBDI/O|rowspan="5"|TBD3.3V|Pin ALT-0|TBD
|-
|Pin ALT-1J2.59||IO_L11N_T1_SRCC_34||FPGA.IO_L11N_T1_SRCC_34||U15||BANK34||I/O||3.3V||TBD
|-
|Pin ALTJ2.61||DGND||DGND||-2|TBD|||||||
|-
|Pin ALT-J2.63||IO_L10P_T1_34||FPGA.IO_L10P_T1_34||V15||BANK34||I/O||3.3V||TBD
|-
|Pin ALT-5J2.65||IO_L10N_T1_34||FPGA.IO_L10N_T1_34||W15||BANK34||I/O||3.3V||TBD
|-
|rowspan="5"|J1J2.6167|rowspan="5"|TBDIO_25_34|rowspan="5"|TBDFPGA.IO_25_34|rowspan="5"|TBDT19|rowspan="5"|TBDBANK34|rowspan="5"|TBDI/O|rowspan="5"|TBD3.3V|Pin ALT-0|TBD
|-
|Pin ALT-1J2.69||IO_0_34||FPGA.IO_0_34||R19||BANK34||I/O||3.3V||TBD
|-
|Pin ALTJ2.71||DGND||DGND||-2|TBD|||G||||
|-
|Pin ALTJ2.73||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ2.75||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J2.6377|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ2.79||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ2.81||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ2.83||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ2.85||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J2.6587|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ2.89||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ2.91||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALT-J2.93||RTC_32KHZ||RTC.32KHZ||1||||O||3.3V||TBDIt can be left open if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
|-
|Pin ALT-5J2.95|TBD|RTC_RST||RTC.~RST ||4||||I/O||3.3V||It can be left open if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
|-
|rowspan="5"|J1J2.6797|rowspan="5"|TBDXADC_VN_R|rowspan="5"|TBDFPGA.VN_0|rowspan="5"|TBDL10|rowspan="5"|TBD|rowspan="5"|TBDA / I|rowspan="5"|TBDVREFP|Pin ALTSee [[BELK-TN-0012: Using XADC signal module|TBDBELK-TN-012 Using XADC signal module]]
|-
|Pin ALTJ2.99||XADC_VP_R||FPGA.VP_0||K9||||A / I||VREFP|See [[BELK-1TN-012: Using XADC signal module|TBDBELK-TN-012 Using XADC signal module]]
|-
|Pin ALTJ2.101||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALT-J2.103||CONN_SPI_RSTn||NOR.~RESET/RFU ||A4||||||3.3V||TBD
|-
|Pin ALT-5J2.105|TBD|CAN_L||CAN.L||6||||I/O||3.3V||For further details, please refer to the Texas Instruments SN65HVD232 datasheet.
|-
|rowspan="5"|J1J2.69107|rowspan="5"|TBDCAN_H|rowspan="5"|TBDCAN.H|rowspan="5"|TBD7|rowspan="5"|TBD|rowspan="5"|TBDI/O|rowspan="5"|TBD3.3V|Pin ALT-0|TBDFor further details, please refer to the Texas Instruments SN65HVD232 datasheet.
|-
|Pin ALTJ2.109||DGND||DGND||-1|TBD|||G||||
|-
|Pin ALTJ2.111||RTC_INT/SQW||RTC.RTC_INT/SQW||3||||I/O||3.3V|| It can be left open if not used. When used, a proper pull-2|TBDup resistor is required on the carrier board. For further details, please refer to the Maxim Integrated DS3232 datasheet.
|-
|Pin ALT-J2.113||RTC_VBAT||RTC.VBAT||6||||S||3.0V||TBDConnect to ground if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
|-
|Pin ALTJ2.115||VBAT||CPU.VCCBATT_0||F11|| ||S|| ||This pin is connected to the VCCBATT_0 (for the battery-backed RAM -5|TBDBBRAM) pin of the Zynq SOC. For additional information, please refer to the Zynq datasheet and TRM.
|-
|rowspan="5"|J1J2.71117|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBDG|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ2.119||3.3VIN||+3.3 V||-1|TBD|||S||||
|-
|Pin ALTJ2.121||3.3VIN||+3.3 V||-2|TBD|||S||||
|-
|Pin ALTJ2.123||3.3VIN||+3.3 V||-3|TBD|||S||||
|-
|Pin ALTJ2.125||DGND||DGND||-5|TBD|||G||||
|-
|rowspan="5"|J1J2.73127|rowspan="5"|TBD3.3VIN|rowspan="5"|TBD+3.3 V|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBDS|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ2.129||3.3VIN||+3.3 V||-1|TBD|||S||||
|-
|Pin ALTJ2.131||3.3VIN||+3.3 V||-2|TBD|||S||||
|-
|Pin ALTJ2.133||3.3VIN||+3.3 V||-3|TBD|||S||||
|-
|Pin ALTJ2.135||3.3VIN||+3.3 V||-5|TBD|||S||||
|-
|rowspan="5"|J1J2.75137|rowspan="5"|TBD3.3VIN|rowspan="5"|TBD+3.3 V|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBDS|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ2.139||DGND||DGND||-1|TBD|||G||||
|-
|} ==SOM J2 EVEN pins (2 to 140) declaration== {| class="wikitable" {| {{table}}| style="background:#f0f0f0;" align="center" |'''Pin'''| style="background:#f0f0f0;" align="center" |'''Pin ALT-2Name'''| style="background:#f0f0f0;" align="center" |'''Internal Connections'''| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''| style="background:#f0f0f0;" align="center" |'''Supply Group'''| style="background:#f0f0f0;" align="center" |'''Type'''| style="background:#f0f0f0;" align="center" |'''Voltage'''|TBDstyle="background:#f0f0f0;" align="center" |'''Note'''
|-
|Pin ALTJ2.2||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-5J2.4||IO_L9P_T1_DQS_34||FPGA.IO_L9P_T1_DQS_34||T16||BANK34||I/O||3.3V||TBD
|-
|rowspan="5"|J1J2.776|rowspan="5"|TBDIO_L9N_T1_DQS_34|rowspan="5"|TBDFPGA.IO_L9N_T1_DQS_34|rowspan="5"|TBDU17|rowspan="5"|TBDBANK34|rowspan="5"|TBDI/O|rowspan="5"|TBD3.3V|Pin ALT-0|TBD
|-
|Pin ALT-1J2.8||IO_L7P_T1_34||FPGA.IO_L7P_T1_34||Y16||BANK34||I/O||3.3V||TBD
|-
|Pin ALT-2J2.10||IO_L7N_T1_34||FPGA.IO_L7N_T1_34||Y17||BANK34||I/O||3.3V||TBD
|-
|Pin ALTJ2.12||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-5J2.14||IO_L5P_T0_34||FPGA.IO_L5P_T0_34||T14||BANK34||I/O||3.3V||TBD
|-
|rowspan="5"|J1J2.7916|rowspan="5"|TBDIO_L5N_T0_34|rowspan="5"|TBDFPGA.IO_L5N_T0_34|rowspan="5"|TBDT15|rowspan="5"|TBDBANK34|rowspan="5"|TBDI/O|rowspan="5"|TBD3.3V|Pin ALT-0|TBD
|-
|Pin ALT-1J2.18||IO_L4P_T0_34||FPGA.IO_L4P_T0_34||V12||BANK34||I/O||3.3V||TBD
|-
|Pin ALT-2J2.20||IO_L4N_T0_34||FPGA.IO_L4N_T0_34||W13||BANK34||I/O||3.3V||TBD
|-
|Pin ALTJ2.22||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-5J2.24||IO_L24P_T3_34||FPGA.IO_L24P_T3_34||P15||BANK34||I/O||3.3V||TBD
|-
|rowspan="5"|J1J2.8126|rowspan="5"|TBDIO_L24N_T3_34|rowspan="5"|TBDFPGA.IO_L24N_T3_34|rowspan="5"|TBDP16|rowspan="5"|TBDBANK34|rowspan="5"|TBDI/O|rowspan="5"|TBD3.3V|Pin ALT-0|TBD
|-
|Pin ALT-1J2.28||IO_L23P_T3_34||FPGA.IO_L23P_T3_34||N17||BANK34||I/O||3.3V||TBD
|-
|Pin ALT-2J2.30||IO_L23N_T3_34||FPGA.IO_L23N_T3_34||P18||BANK34||I/O||3.3V||TBD
|-
|Pin ALTJ2.32||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-5J2.34||IO_L20P_T3_34||FPGA.IO_L20P_T3_34||T17||BANK34||I/O||3.3V||TBD
|-
|rowspan="5"|J1J2.8336|rowspan="5"|TBDIO_L20N_T3_34|rowspan="5"|TBDFPGA.IO_L20N_T3_34|rowspan="5"|TBDR18|rowspan="5"|TBDBANK34|rowspan="5"|TBDI/O|rowspan="5"|TBD3.3V|Pin ALT-0|TBD
|-
|Pin ALT-1J2.38||IO_L1P_T0_34||FPGA.IO_L1P_T0_34||T11||BANK34||I/O||3.3V||TBD
|-
|Pin ALT-2J2.40||IO_L1N_T0_34||FPGA.IO_L1N_T0_34||T10||BANK34||I/O||3.3V||TBD
|-
|Pin ALTJ2.42||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-5J2.44||IO_L17P_T2_34||FPGA.IO_L17P_T2_34||Y18||BANK34||I/O||3.3V||TBD
|-
|rowspan="5"|J1J2.8546|rowspan="5"|TBDIO_L17N_T2_34|rowspan="5"|TBDFPGA.IO_L17N_T2_34|rowspan="5"|TBDY19|rowspan="5"|TBDBANK34|rowspan="5"|TBDI/O|rowspan="5"|TBD3.3V|Pin ALT-0|TBD
|-
|Pin ALT-1J2.48||IO_L16P_T2_34||FPGA.IO_L16P_T2_34||V20||BANK34||I/O||3.3V||TBD
|-
|Pin ALT-2J2.50||IO_L16N_T2_34||FPGA.IO_L16N_T2_34||W20||BANK34||I/O||3.3V||TBD
|-
|Pin ALTJ2.52||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-5J2.54||IO_L14P_T2_SRCC_34||FPGA.IO_L14P_T2_SRCC_34||N20||BANK34||I/O||3.3V||TBD
|-
|rowspan="5"|J1J2.8756|rowspan="5"|TBDIO_L14N_T2_SRCC_34|rowspan="5"|TBDFPGA.IO_L14N_T2_SRCC_34|rowspan="5"|TBDP20|rowspan="5"|TBDBANK34|rowspan="5"|TBDI/O|rowspan="5"|TBD3.3V|Pin ALT-0|TBD
|-
|Pin ALTJ2.58||DGND||DGND||-1|TBD|||G||||
|-
|Pin ALT-2J2.60||IO_L12P_T1_MRCC_34||FPGA.IO_L12P_T1_MRCC_34||U18||BANK34||I/O||3.3V||TBD
|-
|Pin ALT-J2.62||IO_L12N_T1_MRCC_34||FPGA.IO_L12N_T1_MRCC_34||U19||BANK34||I/O||3.3V||TBD
|-
|Pin ALTJ2.64||DGND||DGND||-5|TBD|||G||||
|-
|rowspan="5"|J1J2.8966|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ2.68||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ2.70||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ2.72||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ2.74||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J2.9176|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ2.78||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALT-2J2.80||JTAG_TDO||CPU.TDO_0||F6||||||||TBD
|-
|Pin ALT-3J2.82||JTAG_TDI||CPU.TDI_0||G6||||||||TBD
|-
|Pin ALT-5J2.84||JTAG_TMS||CPU.TMS_0||J6||||||||TBD
|-
|rowspan="5"|J1J2.9386|rowspan="5"|TBDJTAG_TCK|rowspan="5"|TBDCPU.TCK_0|rowspan="5"|TBDF9|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ2.88||DGND||DGND||-1|TBD|||G||||
|-
|Pin ALT-2J2.90|TBD|FPGA_INIT_B||FPGA.INIT_B_0||R10||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]
|-
|Pin ALTJ2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||L6||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]] (10 kΩ pull-3|TBDup resistor is already mounted on BORA module)
|-
|Pin ALT-5J2.94|TBD|FPGA_DONE||FPGA.DONE_0||R11||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]
|-
|rowspan="5"J2.96|J1.95|rowspan="5"WD_SET2|TBD|rowspan="5"WDT.SET2|TBD|rowspan="5"6|TBD|rowspan="5"|TBD|rowspan="5"I|TBD|rowspan="5"3.3V|TBD|Pin ALTInternal 10K pull-0|TBDup. For further details, please refer to the Maxim Integrated MAX6373 datasheet.
|-
|Pin ALTJ2.98||WD_SET1||WDT.SET1||5||||I||3.3V||Internal 10K pull-1|TBDup. For further details, please refer to the Maxim Integrated MAX6373 datasheet.
|-
|Pin ALTJ2.100||WD_SET0||WDT.SET0||4||||I||3.3V||Internal 10K pull-2|TBDdown. For further details, please refer to the Maxim Integrated MAX6373 datasheet.
|-
|Pin ALTJ2.102||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-5J2.104|TBD|PS_MIO50_501||CPU.PS_MIO50_501<br>USBOTG.RESETB||B13<br>22||BANK501||I/O||1.8V|| For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(Bora)#PS_MIO50_501]]
|-
|rowspan="5"J2.106|J1.97|rowspan="5"PS_MIO51_501|TBD|rowspan="5"CPU.PS_MIO51_501<br>ETHPHY1GB.RESET_N|TBD|rowspan="5"B9<br>42|TBD|rowspan="5"BANK501|TBD|rowspan="5"I/O|TBD|rowspan="5"1.8V|TBD|Pin ALT-0For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO51_501_.28J2.106.29 |TBDReset_scheme_(Bora)#PS_MIO51_501]]
|-
|Pin ALT-1J2.108|TBD|BOARD_PGOOD||PSUSWITCHFPGABANK13.ON<br>PSUSWITCHFPGABANK35.ON<br>PSUSWITCHFPGABANK500/34.ON<br>PSUSWITCHFPGABANK501.ON<br>DDRVREFREGULATOR.PGOOD||3<br>3<br>3<br>3<br>9||||O||3.3V||For further details, please refer to [[Power (Bora/BoraLite)|Power Supply (Bora)]]
|-
|Pin ALTJ2.110||CB_PWR_GOOD ||1V0REGULATOR.ENABLE ||-2|TBD|||I||3.3V||For further details, please refer to [[Power (Bora/BoraLite)|Power Supply (Bora)]]
|-
|Pin ALT-3J2.112|TBD|SYS_RSTN||CPU.PS_SRST_B_501<br>MTR.~RST||B10<br>5||||I||1.8V||For further details, please refer to [[Reset scheme (Bora/BoraLite)#Reset signals|Reset signals]]
|-
|Pin ALT-5J2.114|TBD|PORSTN||CPU.PS_POR_B_500||C7||||I/O||3.3V||For further details, please refer to [[Reset scheme (Bora/BoraLite)#Reset signals|Reset signals]]
|-
|rowspan="5"J2.116|J1.99|rowspan="5"MRSTN|TBD|rowspan="5"MTR.MR|TBD|rowspan="5"6|TBD|rowspan="5"|TBD|rowspan="5"I|TBD|rowspan="5"3.3V|TBD|Pin ALT-0For further details, please refer to [[Reset scheme (Bora/BoraLite)#Reset signals|TBDReset signals]]
|-
|Pin ALTJ2.118||DGND||DGND||-1|TBD|||G||||
|-
|Pin ALTJ2.120||3.3VIN||+3.3 V||-2|TBD|||S||||
|-
|Pin ALTJ2.122||3.3VIN||+3.3 V||-3|TBD|||S||||
|-
|Pin ALTJ2.124||DGND||DGND||-5|TBD|||G||||
|-
|rowspan="5"|J1J2.101126|rowspan="5"|TBD3.3VIN|rowspan="5"|TBD+3.3 V|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBDS|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ2.128||3.3VIN||+3.3 V||-1|TBD|||S||||
|-
|Pin ALTJ2.130||3.3VIN||+3.3 V||-2|TBD|||S||||
|-
|Pin ALTJ2.132||3.3VIN||+3.3 V||-3|TBD|||S||||
|-
|Pin ALTJ2.134||3.3VIN||+3.3 V||-5|TBD|||S||||
|-
|rowspan="5"|J1J2.103136|rowspan="5"|TBD3.3VIN|rowspan="5"|TBD+3.3 V|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBDS|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ2.138||3.3VIN||+3.3 V||-1|TBD|||S||||
|-
|Pin ALTJ2.140||DGND||DGND||-2|TBD|||G||||
|-
|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.105|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.107|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.109}|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-SOM J3 ODD pins (1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.111|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.113|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.115|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.117|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.119|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.121|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.123|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.125|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.127|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.129|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.131|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.133|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.135|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.137|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.to 139|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan)declaration="5"|J1.141|rowspan="5"|TBD|rowspan="5"|TBD{|rowspanclass="5wikitable"{|TBD{{table}}|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.143|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|'''Pin ALT-3|TBD|-|Pin ALT-5|TBD|-'''|rowspanstyle="5"|J1.145|rowspan=background:#f0f0f0;"5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspanalign="5center"|TBD|Pin ALT-0|TBD|-|'''Pin ALT-1|TBD|-Name'''|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspanstyle="5background:#f0f0f0;"|J1.147|rowspanalign="5center"|TBD'''Internal Connections'''|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD'''Ball/pin #'''|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD'''Supply Group'''|rowspanstyle="5background:#f0f0f0;"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspanalign="5center"|J1.149'''Type'''|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD'''Voltage'''|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.151|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.153|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.155|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.157|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.159|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.161|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.163|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.165|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.167|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.169|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.171|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.173|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.175|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD'''Note'''
|-
|rowspan="5"|J1J3.1771|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.3||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.5||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ3.7||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.9||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.17911|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.13||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.15||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ3.17||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.19||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.18121|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.23||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.25||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ3.27||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.29||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.18331|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.33||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.35||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ3.37||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.39||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.18541|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.43||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.45||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ3.47||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.49||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.18751|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.53||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.55||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ3.57||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.59||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.18961|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.63||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.65||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ3.67||DGND||DGND||-3|TBD|||||||
|-
|Pin ALTJ3.69||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.19171|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.73||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.75||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ3.77||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.79||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.19381|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.83||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.85||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ3.87||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.89||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.19591|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.93||DGND||DGND||-1|TBD|||G||||
|-
|Pin ALT-2J3.95|TBD|VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|Pin ALT-3J3.97|TBD|VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|Pin ALT-5J3.99|TBD|VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|rowspan="5"|J1J3.197101|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBDG|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.103||DGND||DGND||-1|TBD|||G||||
|-
|Pin ALT-2J3.105|TBD|IO_L21P_T3_DQS_13||FPGA.IO_L21P_T3_DQS_13||V11||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-3J3.107|TBD|IO_L21N_T3_DQS_13||FPGA.IO_L21N_T3_DQS_13||V10||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALTJ3.109||DGND||DGND||-5|TBD|||G||||
|-
|rowspan="5"|J1J3.199111|rowspan="5"|TBDIO_L19P_T3_13|rowspan="5"|TBDFPGA.IO_L19P_T3_13|rowspan="5"|TBDT5|rowspan="5"|TBDBANK13|rowspan="5"|TBDI/O|rowspan="5"|TBDU.D.|Pin ALT-0|TBDNot available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-1J3.113|TBD|IO_L19N_T3_VREF_13||FPGA.IO_L19N_T3_VREF_13||U5||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALTJ3.115||DGND||DGND||-2|TBD|||G||||
|-
|Pin ALT-3J3.117|TBD|IO_L18P_T2_13||FPGA.IO_L18P_T2_13||W11||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-5J3.119|TBD|IO_L18N_T2_13||FPGA.IO_L18N_T2_13||Y11||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|rowspan="5"|J1J3.201121|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBDG|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.123|TBD|IO_L16P_T2_13||FPGA.IO_L16P_T2_13||W10||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-2J3.125|TBD|IO_L16N_T2_13||FPGA.IO_L16N_T2_13||W9||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALTJ3.127||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-5J3.129|TBD|IO_L14P_T2_SRCC_13||FPGA.IO_L14P_T2_SRCC_13||Y9||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|rowspan="5"|J1J3.203131|rowspan="5"|TBDIO_L14N_T2_SRCC_13|rowspan="5"|TBDFPGA.IO_L14N_T2_SRCC_13|rowspan="5"|TBDY8|rowspan="5"|TBDBANK13|rowspan="5"|TBDI/O|rowspan="5"|TBDU.D.|Pin ALT-0|TBDNot available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALTJ3.133||DGND||DGND||-1|TBD|||G||||
|-
|Pin ALT-2J3.135|TBD|IO_L12P_T1_MRCC_13||FPGA.IO_L12P_T1_MRCC_13||T9||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-3J3.137|TBD|IO_L12N_T1_MRCC_13||FPGA.IO_L12N_T1_MRCC_13||U10||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALTJ3.139||DGND||DGND||-5|TBD|||G||||
|-
|}
==Pinout Table SOM J3 EVEN pins (2 to 140) declaration ==
{| class="wikitable" ! latexfontsize="scriptsize"{| Pin ! latexfontsize="scriptsize"| Pin Name{{table}}! latexfontsize="scriptsize"| Internal Connections ! latexfontsizestyle="scriptsize"| Ball/pin background:# ! latexfontsize="scriptsize"| Voltage domain! latexfontsize="scriptsize"| Type ! latexfontsize="scriptsize"| Notes! colspan="2" latexfontsize="scriptsize"| Alternative Functions|-|rowspan="5f0f0f0;"|J1.1|rowspanalign="5center"|SD2_CMD|rowspan="5"|CPU.SD2_CMD|rowspan="5"|F19|rowspan="5"|AXEL_IO_3V3|rowspan="5"|IO|rowspan="5"|Notes|Pin ALT-0|SD2_CMD|-|Pin ALT-1|ECSPI5_MOSI|-|'''Pin ALT-2'''|KEY_ROW5|-|Pin ALT-3|AUD4_RXC|-|Pin ALT-5|GPIO1_IO11|-|rowspanstyle="5background:#f0f0f0;"|J1.3|rowspanalign="5center"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|'''Pin ALT-0Name'''|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspanstyle="5background:#f0f0f0;"|J1.5|rowspanalign="5center"|TBD'''Internal Connections'''|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD'''Ball/pin #'''|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD'''Supply Group'''|rowspanstyle="5background:#f0f0f0;"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspanalign="5center"|J1.7'''Type'''|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD'''Voltage'''|rowspanstyle="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.9|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.11|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.13|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.15|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.17|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.19|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.21|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.23|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.25|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.27|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.29|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.31|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.33|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.35|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.37|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.39|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.31|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.33|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.35|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.37|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.39|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.41|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.43|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.45|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.47|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.49|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.51|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.53|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.55|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.57|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.59|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.61|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.63|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.65|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.67|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.69|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.71|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.73|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.75|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.77|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.79|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.81|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.83|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.85|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.87|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.89|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.91|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.93|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.95|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.97|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.99|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.101|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.103|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.105|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.107|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.109|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.111|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.113|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.115|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.117|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.119|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.121|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.123|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.125|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.127|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.129|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.131|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD'''Note'''
|-
|Pin ALTJ3.2||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.1334|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.6||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.8||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ3.10||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.12||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.13514|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.16||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.18||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ3.20||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.22||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.13724|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.26||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.28||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ3.30||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.32||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.13934|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.36||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.38||N.C.||Not Connected||-2|TBD|||||||
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|Pin ALTJ3.40||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.42||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.14144|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.46||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.48||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ3.50||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.52||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.14354|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.56||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.58||N.C.||Not Connected||-2|TBD|||||||
|-
|Pin ALTJ3.60||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.62||N.C.||Not Connected||-5|TBD|||||||
|-
|rowspan="5"|J1J3.14564|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ3.66||N.C.||Not Connected||-1|TBD|||||||
|-
|Pin ALTJ3.68||DGND||DGND||-2|TBD|||G||||
|-
|Pin ALTJ3.70||N.C.||Not Connected||-3|TBD|||||||
|-
|Pin ALTJ3.72||MON_VCCPLL||n.a.||-5|TBD||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|rowspan="5"|J1J3.14774|rowspan="5"|TBDMON_XADC_VCC|rowspan="5"|TBDn.a.|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBDBy default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALTJ3.76||MON_FPGA_VDDIO_BANK35||n.a.||-1|TBD||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALTJ3.78||MON_FPGA_VDDIO_BANK34||n.a.||-2|TBD||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALTJ3.80||MON_FPGA_VDDIO_BANK13||n.a.||-3|TBD||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALTJ3.82||MON_1.8V_IO||n.a.||-5|TBD||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|rowspan="5"|J1J3.14984|rowspan="5"|TBDMON_3.3V|rowspan="5"|TBDn.a.|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBDBy default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALTJ3.86||MON_1V2_ETH||n.a.||-1|TBD||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALTJ3.88||MON_VDDQ_1V5||n.a.||-2|TBD||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALTJ3.90||MON_1.8V||n.a.||-3|TBD||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALTJ3.92||MON_1.0V||n.a.||-5|TBD||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|rowspan="5"|J1J3.15194|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBDG|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.96|TBD|VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|Pin ALT-2J3.98|TBD|VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|Pin ALT-3J3.100|TBD|IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||V5||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALTJ3.102||DGND||DGND||-5|TBD|||G||||
|-
|rowspan="5"|J1J3.153104|rowspan="5"|TBDIO_L22P_T3_13|rowspan="5"|TBDFPGA.IO_L22P_T3_13|rowspan="5"|TBDV6|rowspan="5"|TBDBANK13|rowspan="5"|TBDI/O|rowspan="5"|TBDU.D.|Pin ALT-0|TBDNot available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-1J3.106|TBD|IO_L22N_T3_13||FPGA.IO_L22N_T3_13||W6||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALTJ3.108||DGND||DGND||-2|TBD|||G||||
|-
|Pin ALT-3J3.110|TBD|IO_L20P_T3_13||FPGA.IO_L20P_T3_13||Y12||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-5J3.112|TBD|IO_L20N_T3_13||FPGA.IO_L20N_T3_13||Y13||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|rowspan="5"|J1J3.155114|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBDG|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.116|TBD|IO_L17P_T2_13||FPGA.IO_L17P_T2_13||U9||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-2J3.118|TBD|IO_L17N_T2_13||FPGA.IO_L17N_T2_13||U8||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALTJ3.120||DGND||DGND||-3|TBD|||G||||
|-
|Pin ALT-5J3.122|TBD|IO_L15P_T2_DQS_13||FPGA.IO_L15P_T2_DQS_13||V8||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|rowspan="5"|J1J3.157124|rowspan="5"|TBDIO_L15N_T2_DQS_13|rowspan="5"|TBDFPGA.IO_L15N_T2_DQS_13|rowspan="5"|TBDW8|rowspan="5"|TBDBANK13|rowspan="5"|TBDI/O|rowspan="5"|TBDU.D.|Pin ALT-0|TBDNot available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALTJ3.126||DGND||DGND||-1|TBD|||G||||
|-
|Pin ALT-2J3.128|TBD|IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y7||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-3J3.130|TBD|IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y6||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALTJ3.132||DGND||DGND||-5|TBD|||G||||
|-
|rowspan="5"|J1J3.159134|rowspan="5"|TBDIO_L11P_T1_SRCC_13|rowspan="5"|TBDFPGA.IO_L11P_T1_SRCC_13|rowspan="5"|TBDU7|rowspan="5"|TBDBANK13|rowspan="5"|TBDI/O|rowspan="5"|TBDU.D.|Pin ALT-0|TBDNot available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-1J3.136|TBD|IO_L11N_T1_SRCC_13||FPGA.IO_L11N_T1_SRCC_13||V7||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALTJ3.138||DGND||DGND||-2|TBD|||G||||
|-
|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.161|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.163|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.165|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.167|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.169|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.171|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.173|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.175|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1J3.177|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-140|Pin ALT-1|TBDDGND|-|Pin ALT-2DGND|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5G|TBD|-|rowspan="5"|J1.179|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.181|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.183|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.185|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.187|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.189|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.191|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.193|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.195|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.197|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.199|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.201|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.203|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD
|-
|}
