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Pinout (Bora)

51 bytes added, 10:33, 30 July 2021
Pinout table
Each row in the pinout tables contains the following information:
* {| class="wikitable" style="width:50%;"|-|'''Pin: reference '''| Reference to the connector pin* |-|'''Pin Name: pin ''' | Pin (signal) name on the Bora AxelLite connectors* |-|'''Internal <br>connections: connections ''' | Connections to the Bora components** CPU.<x> : pin connected to CPU (processing system) pad named <x>** FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>** CAN.<x> : pin connected to the CAN transceiver(TI SN65HVD232)** LAN.<x> : pin connected to the LAN PHY(Microchip KSZ9031)** USBNOR.<x> : pin connected to the USB transceiverNOR flash** NAND.<x>: pin connected to the NAND flash NAND** NOR.IO_L<x>: pin connected to the flash NORPL (FPGA)** SV.<x>MTR: pin connected to voltage supervisormonitors** MTRMON_<x>: pin connected to for external voltage monitorsmonitoring|-* |'''Ball/pin #: ''' | Component ball/pin number connected to signal* Supply Group: Power Supply Group|-|'''Voltage''' || I/O voltage levels |-* |'''Type''' | Pin type: pin type** I = Input** O = Output** D = Differential** Z = High impedance** S = Power supply voltage** G = Ground** A = Analog signal* Voltage: I/O voltage levels|-|'''Notes'''|Remarks on special pin characteristics|-|}
==J1 odd pins (1 to 139)==
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