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Pinout (Bora)

103 bytes added, 09:36, 30 July 2021
→‎J1 odd pins (1 to 139)
==Pinout table==
This chapter contains the pinout description of the Bora module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Bora connectors.
 
Each row in the pinout tables contains the following information:
| style="background:#f0f0f0;" align="center" |'''Note'''
|-
|J1.1||DGND||DGND||n.a.-||||G||||
|-
|J1.3||IO_L7P_T1_AD2P_35||FPGA.IO_L7P_T1_AD2P_35||M19||BANK35|||I/O|||
|-
|J1.5||IO_L10P_T1_AD11P_35||FPGA.IO_L10P_T1_AD11P_35||K19||BANK35|||I/O|||
|-
|J1.7||IO_L11P_T1_SRCC_35||FPGA.IO_L11P_T1_SRCC_35||L16||BANK35|||I/O|||
|-
|J1.9||IO_L8N_T1_AD10N_35||FPGA.IO_L8N_T1_AD10N_35||M18||BANK35|||I/O|||
|-
|J1.11||IO_L7N_T1_AD2N_35||FPGA.IO_L7N_T1_AD2N_35||M20||BANK35|||I/O|||
|-
|J1.13||DGND||DGND||n.a.-||||G||||
|-
|J1.15||IO_L9P_T1_DQS_AD3P_35||FPGA.IO_L9P_T1_DQS_AD3P_35||L19||BANK35|||I/O|||
|-
|J1.17||IO_L9N_T1_DQS_AD3N_35||FPGA.IO_L9N_T1_DQS_AD3N_35||L20||BANK35|||I/O|||
|-
|J1.19||DGND||DGND||n.a.-||||G||||
|-
|J1.21||IO_L20P_T3_AD6P_35||FPGA.IO_L20P_T3_AD6P_35||K14||BANK35|||I/O|||
|-
|J1.23||IO_L20N_T3_AD6N_35||FPGA.IO_L20N_T3_AD6N_35||J14||BANK35|||I/O|||
|-
|J1.25||IO_L22P_T3_AD7P_35||FPGA.IO_L22P_T3_AD7P_35||L14||BANK35|||I/O|||
|-
|J1.27||IO_L12N_T1_MRCC_35||FPGA.IO_L12N_T1_MRCC_35||K18||BANK35|||I/O|||
|-
|J1.29||DGND||DGND||n.a.-||||G||||
|-
|J1.31||IO_L21P_T3_DQS_AD14P_35||FPGA.IO_L21P_T3_DQS_AD14P_35||N15||BANK35|||I/O|||
|-
|J1.33||IO_L21N_T3_DQS_AD14N_35||FPGA.IO_L21N_T3_DQS_AD14N_35||N16||BANK35|||I/O|||
|-
|J1.35||DGND||DGND||n.a.-||||G||||
|-
|J1.37||IO_L17N_T2_AD5N_35||FPGA.IO_L17N_T2_AD5N_35||H20||BANK35|||I/O|||
|-
|J1.39||IO_L13N_T2_MRCC_35||FPGA.IO_L13N_T2_MRCC_35||H17||BANK35|||I/O|||
|-
|J1.41||IO_L19P_T3_35||FPGA.IO_L19P_T3_35||H15||BANK35|||I/O|||
|-
|J1.43||IO_L18P_T2_AD13P_35||FPGA.IO_L18P_T2_AD13P_35||G19||BANK35|||I/O|||
|-
|J1.45||IO_L16P_T2_35||FPGA.IO_L16P_T2_35||G17||BANK35|||I/O|||
|-
|J1.47||IO_L15N_T2_DQS_AD12N_35||FPGA.IO_L15N_T2_DQS_AD12N_35||F20||BANK35|||I/O|||
|-
|J1.49||DGND||DGND||n.a.-||||G||||
|-
|J1.51||IO_L2N_T0_AD8N_35||FPGA.IO_L2N_T0_AD8N_35||A20||BANK35|||I/O|||
|-
|J1.53||IO_L1N_T0_AD0N_35||FPGA.IO_L1N_T0_AD0N_35||B20||BANK35|||I/O|||
|-
|J1.55||IO_L5N_T0_AD9N_35||FPGA.IO_L5N_T0_AD9N_35||E19||BANK35|||I/O|||
|-
|J1.57||IO_L5P_T0_AD9P_35||FPGA.IO_L5P_T0_AD9P_35||E18||BANK35|||I/O|||
|-
|J1.59||DGND||DGND||n.a.-||||G||||
|-
|J1.61||IO_L3P_T0_DQS_AD1P_35||FPGA.IO_L3P_T0_DQS_AD1P_35||E17||BANK35|||I/O|||
|-
|J1.63||IO_L3N_T0_DQS_AD1N_35||FPGA.IO_L3N_T0_DQS_AD1N_35||D18||BANK35|||I/O|||
|-
|J1.65||DGND||DGND||n.a.-||||G||||
|-
|J1.67||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||BANK35|S||||User Defined: 1.8V to 3.3V (see [[Programmable logic (Bora)#Introduction|Programmable logic (Bora)]] )
|-
|J1.69||XADC_AGND||FPGA.GNDADC_0||J10||||A / G||||
|-
|J1.71||XADC_AGND||FPGA.GNDADC_0||J10||||A / G||||
|-
|J1.73||PS_MIO45_501 ||CPU.PS_MIO45_501||B15||BANK501|I/O||||1.8V|
|-
|J1.75||PS_MIO44_501||CPU.PS_MIO44_501||F13||BANK501|I/O||||1.8V|
|-
|J1.77||PS_MIO43_501||CPU.PS_MIO43_501||A9||BANK501|I/O||||1.8V|
|-
|J1.79||PS_MIO42_501||CPU.PS_MIO42_501||E12||BANK501|I/O||||1.8V|
|-
|J1.81||PS_MIO41_501||CPU.PS_MIO41_501||C17||BANK501|I/O||||1.8V|
|-
|J1.83||DGND||DGND||n.a.-||||G||||
|-
|J1.85||PS_MIO40_501||CPU.PS_MIO40_501||D14||BANK501|I/O||||1.8V|
|-
|J1.87||ETH_MDIO||CPU.PS_MIO53_501<br>LAN.MDIO||C11<br>37||BANK501|I/O||||1.8V|
|-
|J1.89||ETH_MDC||CPU.PS_MIO12_501<br>LAN.MDC||C10<br>36||BANK501|I/O||||1.8V|
|-
|J1.91||ETH_LED1||LAN.LED1 / PME_N1||17||||||||
|J1.93||ETH_LED2||LAN.LED2||15||||||||
|-
|J1.95||DGND||DGND||n.a.-||||G||||
|-
|J1.97||ETH_TXRX1_M||LAN.TXRXM_B||6||||||||
|J1.99||ETH_TXRX1_P||LAN.TXRXP_B||5||||||||
|-
|J1.101||DGND||DGND||n.a.-||||G||||
|-
|J1.103||ETH_TXRX0_M||LAN.TXRXM_A||3||||||||
|J1.105||ETH_TXRX0_P||LAN.TXRXP_A||2||||||||
|-
|J1.107||DVDDH||LAN.DVDDH||16<br>34<br>40|||||||1.8V|
|-
|J1.109||N.C.||Not Connected||n.a.-||||||||
|-
|J1.111||USBOTG_CPEN||USB.CPEN||7||||||||
|J1.115||OTG_ID||USB.ID||1||||||||
|-
|J1.117||DGND||DGND||n.a.-||||G||||
|-
|J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500||A6||BANK500|||||3.3V| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|J1.121||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500||B7||BANK500|||||3.3V| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|J1.123||SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500||D6||BANK500|||||3.3V| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500||B8||BANK500|||||3.3V| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|J1.127||DGND||DGND||n.a.-||||G||||
|-
|J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500||A5||BANK500|||||3.3V| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|J1.131||NAND_BUSY||CPU.PS_MIO14_500||C5||BANK500|||||3.3V|
|-
|J1.133||PS_MIO15_500||CPU.PS_MIO15_500<br>WDT.WDI||C8<br>1||BANK500|||||3.3V|See also [[Watchdog_(Bora)|this page]]
|-
|J1.135||N.C.||Not Connected||n.a.-||||||||
|-
|J1.137||MEM_WPN||NAND.WP - NOR.WP/IO2||19 - C4||||||||
|-
|J1.139||DGND||DGND||n.a.-||||G||||
|-
|}
| style="background:#f0f0f0;" align="center" |'''Note'''
|-
|J1.2||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||BANK35||S||||
|-
|J1.4||DGND||DGND||n.a.-||||G||||
|-
|J1.6||IO_L10N_T1_AD11N_35||FPGA.IO_L10N_T1_AD11N_35||J19|||BANK35|||||
|-
|J1.8||IO_L12P_T1_MRCC_35||FPGA.IO_L12P_T1_MRCC_35||K17|||BANK35|||||
|-
|J1.10||IO_L11N_T1_SRCC_35||FPGA.IO_L11N_T1_SRCC_35||L17|||BANK35|||||
|-
|J1.12||IO_L8P_T1_AD10P_35||FPGA.IO_L8P_T1_AD10P_35||M17|||BANK35|||||
|-
|J1.14||DGND||DGND||n.a.-||||G||||
|-
|J1.16||IO_L24N_T3_AD15N_35||FPGA.IO_L24N_T3_AD15N_35||J16|||BANK35|||||
|-
|J1.18||IO_25_35||FPGA.IO_25_35||J15|||BANK35|||||
|-
|J1.20||IO_L24P_T3_AD15P_35||FPGA.IO_L24P_T3_AD15P_35||K16|||BANK35|||||
|-
|J1.22||IO_L23N_T3_35||FPGA.IO_L23N_T3_35||M15|||BANK35|||||
|-
|J1.24||DGND||DGND||n.a.-||||G||||
|-
|J1.26||IO_L22N_T3_AD7N_35||FPGA.IO_L22N_T3_AD7N_35||L15|||BANK35|||||
|-
|J1.28||IO_L23P_T3_35||FPGA.IO_L23P_T3_35||M14|||BANK35|||||
|-
|J1.30||DGND||DGND||n.a.-||||G||||
|-
|J1.32||IO_L17P_T2_AD5P_35||FPGA.IO_L17P_T2_AD5P_35||J20|||BANK35|||||
|-
|J1.34||IO_L14P_T2_AD4P_SRCC_35||FPGA.IO_L14P_T2_AD4P_SRCC_35||J18|||BANK35|||||
|-
|J1.36||IO_L14N_T2_AD4N_SRCC_35||FPGA.IO_L14N_T2_AD4N_SRCC_35||H18|||BANK35|||||
|-
|J1.38||DGND||DGND||n.a.-||||G||||
|-
|J1.40||IO_L13P_T2_MRCC_35||FPGA.IO_L13P_T2_MRCC_35||H16|||BANK35|||||
|-
|J1.42||IO_L18N_T2_AD13N_35||FPGA.IO_L18N_T2_AD13N_35||G20|||BANK35|||||
|-
|J1.44||IO_L16N_T2_35||FPGA.IO_L16N_T2_35||G18|||BANK35|||||
|-
|J1.46||IO_L15P_T2_DQS_AD12P_35||FPGA.IO_L15P_T2_DQS_AD12P_35||F19|||BANK35|||||
|-
|J1.48||DGND||DGND||n.a.-||||G||||
|-
|J1.50||IO_L1P_T0_AD0P_35||FPGA.IO_L1P_T0_AD0P_35||C20|||BANK35|||||
|-
|J1.52||IO_L2P_T0_AD8P_35||FPGA.IO_L2P_T0_AD8P_35||B19|||BANK35|||||
|-
|J1.54||IO_L4N_T0_35||FPGA.IO_L4N_T0_35||D20|||BANK35|||||
|-
|J1.56||IO_L4P_T0_35||FPGA.IO_L4P_T0_35||D19|||BANK35|||||
|-
|J1.58||IO_L6P_T0_35||FPGA.IO_L6P_T0_35||F16|||BANK35|||||
|-
|J1.60||DGND||DGND||n.a.-||||G||||
|-
|J1.62||IO_L6N_T0_VREF_35||FPGA.IO_L6N_T0_VREF_35||F17|||BANK35|||||
|-
|J1.64||IO_L19N_T3_VREF_35||FPGA.IO_L19N_T3_VREF_35||G15|||BANK35|||||
|-
|J1.66||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16|||BANK35|||||
|-
|J1.68||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16|||BANK35|||||
|-
|J1.70||XADC_AGND||FPGA.GNDADC_0||J10||||||||
|J1.74||IO_0_35||FPGA.IO_0_35||G14||||||||
|-
|J1.76||N.C.||Not Connected||n.a.-||||||||
|-
|J1.78||N.C.||Not Connected||n.a.-||||||||
|-
|J1.80||PS_MIO49_501||CPU.PS_MIO49_501||C12||||||||
|J1.84||PS_MIO47_501||CPU.PS_MIO47_501||B14||||||||
|-
|J1.86||DGND||DGND||n.a.-||||G||||
|-
|J1.88||PS_MIO46_501||CPU.PS_MIO46_501||D16||||||||
|J1.90||ETH_INTN||LAN.INT_N / PME_N2||38||||||||
|-
|J1.92||DGND||DGND||n.a.-||||G||||
|-
|J1.94||ETH_TXRX3_M||LAN.TXRXM_D||11||||||||
|J1.96||ETH_TXRX3_P||LAN.TXRXP_D||10||||||||
|-
|J1.98||DGND||DGND||n.a.-||||G||||
|-
|J1.100||ETH_TXRX2_M||LAN.TXRXM_C||8||||||||
|J1.102||ETH_TXRX2_P||LAN.TXRXP_C||7||||||||
|-
|J1.104||DGND||DGND||n.a.-||||G||||
|-
|J1.106||CLK125_NDO||LAN.CLK125_NDO||41||||||||
|-
|J1.108||N.C.||Not Connected||n.a.-||||||||
|-
|J1.110||N.C.||Not Connected||n.a.-||||||||
|-
|J1.112||DGND||DGND||n.a.-||||G||||
|-
|J1.114||USBP1||USB.DP||6||||||||
|J1.116||USBM1||USB.DM||5||||||||
|-
|J1.118||DGND||DGND||n.a.-||||G||||
|-
|J1.120||SPI0_CS0N||CPU.PS_MIO1_500<br>NOR.CS#||A7<br>C2||||||||
|J1.128||NAND_IO5||CPU.PS_MIO10_500<br>NAND.I/O5||E9<br>42||||||||
|-
|J1.130||DGND||DGND||n.a.-||||G||||
|-
|J1.132||NAND_IO6||CPU.PS_MIO11_500<br>NAND.I/O6||C6<br>43||||||||
|J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500<br>NAND.CLE||D8<br>16|||||||| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|J1.140||DGND||DGND||n.a.-||||G||||
|-
|}
| style="background:#f0f0f0;" align="center" |'''Note'''
|-
|J2.1||DGND||DGND||n.a.-||||||||
|-
|J2.3||DGND||DGND||n.a.-||||||||
|-
|J2.5||IO_L8P_T1_34||FPGA.IO_L8P_T1_34||W14||||||||
|J2.11||IO_L6N_T0_VREF_34||FPGA.IO_L6N_T0_VREF_34||R14||||||||
|-
|J2.13||DGND||DGND||n.a.-||||||||
|-
|J2.15||IO_L3P_T0_DQS_PUDC_B_34||FPGA.IO_L3P_T0_DQS_PUDC_B_34||U13|||||| Internally connected to 3V3 via 10K resistor ||
|J2.21||IO_L2N_T0_34||FPGA.IO_L2N_T0_34||U12||||||||
|-
|J2.23||DGND||DGND||n.a.-||||||||
|-
|J2.25||IO_L22P_T3_34||FPGA.IO_L22P_T3_34||W18||||||||
|J2.31||IO_L21N_T3_DQS_34||FPGA.IO_L21N_T3_DQS_34||V18||||||||
|-
|J2.33||DGND||DGND||n.a.-||||||||
|-
|J2.35||IO_L19P_T3_34||CAN.R<br>FPGA.IO_L19P_T3_34||4<br>R16||||||||
|J2.41||IO_L18N_T2_34||FPGA.IO_L18N_T2_34||W16||||||||
|-
|J2.43||DGND||DGND||n.a.-||||||||
|-
|J2.45||IO_L15P_T2_DQS_34||FPGA.IO_L15P_T2_DQS_34||T20||||||||
|J2.47||IO_L15N_T2_DQS_34||FPGA.IO_L15N_T2_DQS_34||U20||||||||
|-
|J2.49||DGND||DGND||n.a.-||||||||
|-
|J2.51||IO_L13P_T1_MRCC_34||FPGA.IO_L13P_T1_MRCC_34||N18||||||||
|J2.53||IO_L13N_T1_MRCC_34||FPGA.IO_L13N_T1_MRCC_34||P19||||||||
|-
|J2.55||DGND||DGND||n.a.-||||||||
|-
|J2.57||IO_L11P_T1_SRCC_34||FPGA.IO_L11P_T1_SRCC_34||U14||||||||
|J2.59||IO_L11N_T1_SRCC_34||FPGA.IO_L11N_T1_SRCC_34||U15||||||||
|-
|J2.61||DGND||DGND||n.a.-||||||||
|-
|J2.63||IO_L10P_T1_34||FPGA.IO_L10P_T1_34||V15||||||||
|J2.69||IO_0_34||FPGA.IO_0_34||R19||||||||
|-
|J2.71||DGND||DGND||n.a.-||||||||
|-
|J2.73||N.C.||Not Connected||n.a.-||||||||
|-
|J2.75||N.C.||Not Connected||n.a.-||||||||
|-
|J2.77||N.C.||Not Connected||n.a.-||||||||
|-
|J2.79||N.C.||Not Connected||n.a.-||||||||
|-
|J2.81||N.C.||Not Connected||n.a.-||||||||
|-
|J2.83||N.C.||Not Connected||n.a.-||||||||
|-
|J2.85||N.C.||Not Connected||n.a.-||||||||
|-
|J2.87||N.C.||Not Connected||n.a.-||||||||
|-
|J2.89||N.C.||Not Connected||n.a.-||||||||
|-
|J2.91||N.C.||Not Connected||n.a.-||||||||
|-
|J2.93||RTC_32KHZ||RTC.32KHZ||1||||||||
|J2.99||XADC_VP_R||FPGA.VP_0||K9||||||||
|-
|J2.101||N.C.||Not Connected||n.a.-||||||||
|-
|J2.103||CONN_SPI_RSTn||NOR.~RESET/RFU ||A4||||||||
|J2.107||CAN_H||CAN.H||7||||||||
|-
|J2.109||DGND||DGND||n.a.-||||||||
|-
|J2.111||RTC_INT/SQW||RTC.RTC_INT/SQW||3|||||||| It can be left open if not used. When used, a proper pull-up resistor is required on the carrier board. For further details, please refer to the Maxim Integrated DS3232 datasheet.
|J2.115||VBAT||CPU.VCCBATT_0||F11|| || || ||This pin is connected to the VCCBATT_0 (for the battery-backed RAM - BBRAM) pin of the Zynq SOC. For additional information, please refer to the Zynq datasheet and TRM.
|-
|J2.117||DGND||DGND||n.a.-||||||||
|-
|J2.119||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.121||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.123||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.125||DGND||DGND||n.a.-||||||||
|-
|J2.127||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.129||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.131||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.133||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.135||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.137||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.139||DGND||DGND||n.a.-||||||||
|-
|}
| style="background:#f0f0f0;" align="center" |'''Note'''
|-
|J2.2||DGND||DGND||n.a.-||||||||
|-
|J2.4||IO_L9P_T1_DQS_34||FPGA.IO_L9P_T1_DQS_34||T16||||||||
|J2.10||IO_L7N_T1_34||FPGA.IO_L7N_T1_34||Y17||||||||
|-
|J2.12||DGND||DGND||n.a.-||||||||
|-
|J2.14||IO_L5P_T0_34||FPGA.IO_L5P_T0_34||T14||||||||
|J2.20||IO_L4N_T0_34||FPGA.IO_L4N_T0_34||W13||||||||
|-
|J2.22||DGND||DGND||n.a.-||||||||
|-
|J2.24||IO_L24P_T3_34||FPGA.IO_L24P_T3_34||P15||||||||
|J2.30||IO_L23N_T3_34||FPGA.IO_L23N_T3_34||P18||||||||
|-
|J2.32||DGND||DGND||n.a.-||||||||
|-
|J2.34||IO_L20P_T3_34||FPGA.IO_L20P_T3_34||T17||||||||
|J2.40||IO_L1N_T0_34||FPGA.IO_L1N_T0_34||T10||||||||
|-
|J2.42||DGND||DGND||n.a.-||||||||
|-
|J2.44||IO_L17P_T2_34||FPGA.IO_L17P_T2_34||Y18||||||||
|J2.50||IO_L16N_T2_34||FPGA.IO_L16N_T2_34||W20||||||||
|-
|J2.52||DGND||DGND||n.a.-||||||||
|-
|J2.54||IO_L14P_T2_SRCC_34||FPGA.IO_L14P_T2_SRCC_34||N20||||||||
|J2.56||IO_L14N_T2_SRCC_34||FPGA.IO_L14N_T2_SRCC_34||P20||||||||
|-
|J2.58||DGND||DGND||n.a.-||||||||
|-
|J2.60||IO_L12P_T1_MRCC_34||FPGA.IO_L12P_T1_MRCC_34||U18||||||||
|J2.62||IO_L12N_T1_MRCC_34||FPGA.IO_L12N_T1_MRCC_34||U19||||||||
|-
|J2.64||DGND||DGND||n.a.-||||||||
|-
|J2.66||N.C.||Not Connected||n.a.-||||||||
|-
|J2.68||N.C.||Not Connected||n.a.-||||||||
|-
|J2.70||N.C.||Not Connected||n.a.-||||||||
|-
|J2.72||N.C.||Not Connected||n.a.-||||||||
|-
|J2.74||N.C.||Not Connected||n.a.-||||||||
|-
|J2.76||N.C.||Not Connected||n.a.-||||||||
|-
|J2.78||N.C.||Not Connected||n.a.-||||||||
|-
|J2.80||JTAG_TDO||CPU.TDO_0||F6||||||||
|J2.86||JTAG_TCK||CPU.TCK_0||F9||||||||
|-
|J2.88||DGND||DGND||n.a.-||||||||
|-
|J2.90||FPGA_INIT_B||FPGA.INIT_B_0||R10||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]
|J2.100||WD_SET0||WDT.SET0||4||||||||
|-
|J2.102||DGND||DGND||n.a.-||||||||
|-
|J2.104||PS_MIO50_501||CPU.PS_MIO50_501<br>USBOTG.RESETB||B13<br>22|||||||| For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(Bora)#PS_MIO50_501]]
|J2.108||BOARD_PGOOD||PSUSWITCHFPGABANK13.ON<br>PSUSWITCHFPGABANK35.ON<br>PSUSWITCHFPGABANK500/34.ON<br>PSUSWITCHFPGABANK501.ON<br>DDRVREFREGULATOR.PGOOD||3<br>3<br>3<br>3<br>9||||||||
|-
|J2.110||CB_PWR_GOOD ||1V0REGULATOR.ENABLE ||n.a.-||||||||
|-
|J2.112||SYS_RSTN||CPU.PS_SRST_B_501<br>MTR.~RST||B10<br>5||||||||
|J2.116||MRSTN||MTR.MR||6||||||||
|-
|J2.118||DGND||DGND||n.a.-||||||||
|-
|J2.120||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.122||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.124||DGND||DGND||n.a.-||||||||
|-
|J2.126||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.128||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.130||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.132||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.134||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.136||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.138||3.3VIN||+3.3 V||n.a.-||||||||
|-
|J2.140||DGND||DGND||n.a.-||||||||
|-
|}
| style="background:#f0f0f0;" align="center" |'''Note'''
|-
|J3.1||N.C.||Not Connected||n.a.-||||||||
|-
|J3.3||N.C.||Not Connected||n.a.-||||||||
|-
|J3.5||N.C.||Not Connected||n.a.-||||||||
|-
|J3.7||N.C.||Not Connected||n.a.-||||||||
|-
|J3.9||N.C.||Not Connected||n.a.-||||||||
|-
|J3.11||N.C.||Not Connected||n.a.-||||||||
|-
|J3.13||N.C.||Not Connected||n.a.-||||||||
|-
|J3.15||N.C.||Not Connected||n.a.-||||||||
|-
|J3.17||N.C.||Not Connected||n.a.-||||||||
|-
|J3.19||N.C.||Not Connected||n.a.-||||||||
|-
|J3.21||N.C.||Not Connected||n.a.-||||||||
|-
|J3.23||N.C.||Not Connected||n.a.-||||||||
|-
|J3.25||N.C.||Not Connected||n.a.-||||||||
|-
|J3.27||N.C.||Not Connected||n.a.-||||||||
|-
|J3.29||N.C.||Not Connected||n.a.-||||||||
|-
|J3.31||N.C.||Not Connected||n.a.-||||||||
|-
|J3.33||N.C.||Not Connected||n.a.-||||||||
|-
|J3.35||N.C.||Not Connected||n.a.-||||||||
|-
|J3.37||N.C.||Not Connected||n.a.-||||||||
|-
|J3.39||N.C.||Not Connected||n.a.-||||||||
|-
|J3.41||N.C.||Not Connected||n.a.-||||||||
|-
|J3.43||N.C.||Not Connected||n.a.-||||||||
|-
|J3.45||N.C.||Not Connected||n.a.-||||||||
|-
|J3.47||N.C.||Not Connected||n.a.-||||||||
|-
|J3.49||N.C.||Not Connected||n.a.-||||||||
|-
|J3.51||N.C.||Not Connected||n.a.-||||||||
|-
|J3.53||N.C.||Not Connected||n.a.-||||||||
|-
|J3.55||N.C.||Not Connected||n.a.-||||||||
|-
|J3.57||N.C.||Not Connected||n.a.-||||||||
|-
|J3.59||N.C.||Not Connected||n.a.-||||||||
|-
|J3.61||N.C.||Not Connected||n.a.-||||||||
|-
|J3.63||N.C.||Not Connected||n.a.-||||||||
|-
|J3.65||N.C.||Not Connected||n.a.-||||||||
|-
|J3.67||DGND||DGND||n.a.-||||||||
|-
|J3.69||N.C.||Not Connected||n.a.-||||||||
|-
|J3.71||N.C.||Not Connected||n.a.-||||||||
|-
|J3.73||N.C.||Not Connected||n.a.-||||||||
|-
|J3.75||N.C.||Not Connected||n.a.-||||||||
|-
|J3.77||N.C.||Not Connected||n.a.-||||||||
|-
|J3.79||N.C.||Not Connected||n.a.-||||||||
|-
|J3.81||N.C.||Not Connected||n.a.-||||||||
|-
|J3.83||N.C.||Not Connected||n.a.-||||||||
|-
|J3.85||N.C.||Not Connected||n.a.-||||||||
|-
|J3.87||N.C.||Not Connected||n.a.-||||||||
|-
|J3.89||N.C.||Not Connected||n.a.-||||||||
|-
|J3.91||N.C.||Not Connected||n.a.-||||||||
|-
|J3.93||DGND||DGND||n.a.-||||||||
|-
|J3.95||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|J3.99||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|J3.101||DGND||DGND||n.a.-||||||||
|-
|J3.103||DGND||DGND||n.a.-||||||||
|-
|J3.105||IO_L21P_T3_DQS_13||FPGA.IO_L21P_T3_DQS_13||V11|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|J3.107||IO_L21N_T3_DQS_13||FPGA.IO_L21N_T3_DQS_13||V10|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.109||DGND||DGND||n.a.-||||||||
|-
|J3.111||IO_L19P_T3_13||FPGA.IO_L19P_T3_13||T5|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|J3.113||IO_L19N_T3_VREF_13||FPGA.IO_L19N_T3_VREF_13||U5|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.115||DGND||DGND||n.a.-||||||||
|-
|J3.117||IO_L18P_T2_13||FPGA.IO_L18P_T2_13||W11|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|J3.119||IO_L18N_T2_13||FPGA.IO_L18N_T2_13||Y11|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.121||DGND||DGND||n.a.-||||||||
|-
|J3.123||IO_L16P_T2_13||FPGA.IO_L16P_T2_13||W10|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|J3.125||IO_L16N_T2_13||FPGA.IO_L16N_T2_13||W9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.127||DGND||DGND||n.a.-||||||||
|-
|J3.129||IO_L14P_T2_SRCC_13||FPGA.IO_L14P_T2_SRCC_13||Y9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|J3.131||IO_L14N_T2_SRCC_13||FPGA.IO_L14N_T2_SRCC_13||Y8|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.133||DGND||DGND||n.a.-||||||||
|-
|J3.135||IO_L12P_T1_MRCC_13||FPGA.IO_L12P_T1_MRCC_13||T9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|J3.137||IO_L12N_T1_MRCC_13||FPGA.IO_L12N_T1_MRCC_13||U10|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.139||DGND||DGND||n.a.-||||||||
|-
|}
| style="background:#f0f0f0;" align="center" |'''Note'''
|-
|J3.2||N.C.||Not Connected||n.a.-||||||||
|-
|J3.4||N.C.||Not Connected||n.a.-||||||||
|-
|J3.6||N.C.||Not Connected||n.a.-||||||||
|-
|J3.8||N.C.||Not Connected||n.a.-||||||||
|-
|J3.10||N.C.||Not Connected||n.a.-||||||||
|-
|J3.12||N.C.||Not Connected||n.a.-||||||||
|-
|J3.14||N.C.||Not Connected||n.a.-||||||||
|-
|J3.16||N.C.||Not Connected||n.a.-||||||||
|-
|J3.18||N.C.||Not Connected||n.a.-||||||||
|-
|J3.20||N.C.||Not Connected||n.a.-||||||||
|-
|J3.22||N.C.||Not Connected||n.a.-||||||||
|-
|J3.24||N.C.||Not Connected||n.a.-||||||||
|-
|J3.26||N.C.||Not Connected||n.a.-||||||||
|-
|J3.28||N.C.||Not Connected||n.a.-||||||||
|-
|J3.30||N.C.||Not Connected||n.a.-||||||||
|-
|J3.32||N.C.||Not Connected||n.a.-||||||||
|-
|J3.34||N.C.||Not Connected||n.a.-||||||||
|-
|J3.36||N.C.||Not Connected||n.a.-||||||||
|-
|J3.38||N.C.||Not Connected||n.a.-||||||||
|-
|J3.40||N.C.||Not Connected||n.a.-||||||||
|-
|J3.42||N.C.||Not Connected||n.a.-||||||||
|-
|J3.44||N.C.||Not Connected||n.a.-||||||||
|-
|J3.46||N.C.||Not Connected||n.a.-||||||||
|-
|J3.48||N.C.||Not Connected||n.a.-||||||||
|-
|J3.50||N.C.||Not Connected||n.a.-||||||||
|-
|J3.52||N.C.||Not Connected||n.a.-||||||||
|-
|J3.54||N.C.||Not Connected||n.a.-||||||||
|-
|J3.56||N.C.||Not Connected||n.a.-||||||||
|-
|J3.58||N.C.||Not Connected||n.a.-||||||||
|-
|J3.60||N.C.||Not Connected||n.a.-||||||||
|-
|J3.62||N.C.||Not Connected||n.a.-||||||||
|-
|J3.64||N.C.||Not Connected||n.a.-||||||||
|-
|J3.66||N.C.||Not Connected||n.a.-||||||||
|-
|J3.68||DGND||DGND||n.a.-||||||||
|-
|J3.70||N.C.||Not Connected||n.a.-||||||||
|-
|J3.72||MON_VCCPLL||n.a.||n.a.-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|J3.74||MON_XADC_VCC||n.a.||n.a.-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|J3.76||MON_FPGA_VDDIO_BANK35||n.a.||n.a.-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|J3.78||MON_FPGA_VDDIO_BANK34||n.a.||n.a.-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|J3.80||MON_FPGA_VDDIO_BANK13||n.a.||n.a.-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|J3.82||MON_1.8V_IO||n.a.||n.a.-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|J3.84||MON_3.3V||n.a.||n.a.-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|J3.86||MON_1V2_ETH||n.a.||n.a.-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|J3.88||MON_VDDQ_1V5||n.a.||n.a.-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|J3.90||MON_1.8V||n.a.||n.a.-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|J3.92||MON_1.0V||n.a.||n.a.-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|J3.94||DGND||DGND||n.a.-||||||||
|-
|J3.96||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|J3.100||IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||V5|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.102||DGND||DGND||n.a.-||||||||
|-
|J3.104||IO_L22P_T3_13||FPGA.IO_L22P_T3_13||V6|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|J3.106||IO_L22N_T3_13||FPGA.IO_L22N_T3_13||W6|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.108||DGND||DGND||n.a.-||||||||
|-
|J3.110||IO_L20P_T3_13||FPGA.IO_L20P_T3_13||Y12|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|J3.112||IO_L20N_T3_13||FPGA.IO_L20N_T3_13||Y13|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.114||DGND||DGND||n.a.-||||||||
|-
|J3.116||IO_L17P_T2_13||FPGA.IO_L17P_T2_13||U9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|J3.118||IO_L17N_T2_13||FPGA.IO_L17N_T2_13||U8|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.120||DGND||DGND||n.a.-||||||||
|-
|J3.122||IO_L15P_T2_DQS_13||FPGA.IO_L15P_T2_DQS_13||V8|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|J3.124||IO_L15N_T2_DQS_13||FPGA.IO_L15N_T2_DQS_13||W8|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.126||DGND||DGND||n.a.-||||||||
|-
|J3.128||IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y7|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|J3.130||IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y6|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.132||DGND||DGND||n.a.-||||||||
|-
|J3.134||IO_L11P_T1_SRCC_13||FPGA.IO_L11P_T1_SRCC_13||U7|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|J3.136||IO_L11N_T1_SRCC_13||FPGA.IO_L11N_T1_SRCC_13||V7|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.138||DGND||DGND||n.a.-||||||||
|-
|J3.140||DGND||DGND||n.a.-||||||||
|-
|}
U0007
Bureaucrats, dave_user, Administrators
8,154
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