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Pinout (Bora)

18,413 bytes removed, 07:55, 30 July 2021
Undo revision 14368 by U0007 (talk)
<section begin=History/>{{InfoBoxTop}}{| style="border-collapse:collapse; "!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History|- !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|X.Y.Z|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD|-|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|[TBD_link X.Y.Z]|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|-|{Applies To Bora}}<section end=History/><section begin=Body/>''TBD: modificare la tabella seguente con le caratteristiche dei pin del SOM'' ''TBD: modificare le due tabelle ODD e EVEN con la mappa completa dei pins'' '''TBD: nella tabella naming conventions, inserire il codice dei vari IC presenti (PMIC, PHY ETH, ecc.)''' ==Connectors and Pinout Table== === Connectors description ===In the following table are described all available connectors integrated on [[BORA]]:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM DDR3 edge connector 204 pin||TE Connectivity 2-2013289-1|-|Jxx|TBD|TBD|TBD|-|Jxx|TBD|TBD|TBD|-|Jxx|TBD|TBD|TBD|-|Jxx|TBD|TBD|TBD|{InfoBoxBottom}}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA pinout specifications. See the images below for reference: [[File:BORA-top.png|500px|thumb|BORA TOP view|none]][[File:BORA-bottom.png|500px|thumb|BORA BOTTOM view|none]] ===Pinout table naming conventions === This chapter contains the pinout description of the BORA module, grouped in two tables (odd and even pins) that report the pin mapping of the ''TBD: connector type'' BORA connector.
==Pinout table==
This chapter contains the pinout description of the Bora module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Bora connectors.
Each row in the pinout tables contains the following information:
{|class="wikitable" style="width* Pin:50%;"|-|'''Pin'''| Reference reference to the connector pin|-|'''* Pin Name''' | Pin : pin (signal) name on the BORA Bora connectors|-|'''* Internal<br>connections''' | Connections : connections to the BORA Bora components** CPU.<x> : pin connected to CPU (processing system) pad named <x>* CAN* FPGA.<x> : pin connected to the CAN transceiver FPGA (''manufacturer'' ''part number''programmable logic)pad named <x>* PMIC* CAN.<x> : pin connected to the Power Manager IC (''manufacturer'' ''part number'')CAN transceiver** LAN.<x> : pin connected to the LAN PHY (''manufacturer'' ''part number'')** USB.<x> : pin connected to the USB transceiver** NAND.<x>: pin connected to the flash NAND** NOR.<x>: pin connected to the flash NOR** SV.<x>: pin connected to voltage supervisor** MTR: pin connected to voltage monitors|-|'''* Ball/pin #''' | : Component ball/pin number connected to signal|-* Supply Group: Power Supply Group|'''Voltage''' || I/O voltage levels |-|'''* Type''' | Pin : pin type:** I = Input** O = Output** D = Differential** Z = High impedance** S = Power supply voltage** G = Ground** A = Analog signal|-|'''Notes'''|Remarks on special pin characteristics|-|'''Pin MUX alternative functions'''|Muxes* Voltage:* Pin ALT-0* ...* Pin ALT-NThe number of functions depends on platform|-|}I/O voltage levels
==Pinout Table ODD J1 odd pins declaration (1 to 139)==
{| class="wikitable" {| {{table}}! latexfontsize| style="background:#f0f0f0;" align="scriptsizecenter"| '''Pin '''! latexfontsize| style="background:#f0f0f0;" align="scriptsizecenter"| '''Pin Name'''! latexfontsize| style="background:#f0f0f0;" align="scriptsizecenter"| '''Internal Connections '''! latexfontsize| style="background:#f0f0f0;" align="scriptsizecenter"| '''Ball/pin # '''! latexfontsize| style="background:#f0f0f0;" align="scriptsizecenter"| Voltage domain'''Supply Group'''! latexfontsize| style="background:#f0f0f0;" align="scriptsizecenter"| '''Type '''! latexfontsize| style="background:#f0f0f0;" align="scriptsizecenter"| Notes'''Voltage'''! colspan| style="2background:#f0f0f0;" latexfontsizealign="scriptsizecenter"| Alternative Functions'''Note'''
|-
|rowspan="5"|J1.1|rowspan="5"|SD2_CMDDGND|rowspan="5"|CPU.SD2_CMDDGND|rowspan="5"|F19n.a.|rowspan="5"|AXEL_IO_3V3|rowspan="5"|IO|rowspan="5"|Notes|Pin ALT-0|SD2_CMD
|-
|Pin ALT-1J1.3||IO_L7P_T1_AD2P_35||FPGA.IO_L7P_T1_AD2P_35||M19||||||||ECSPI5_MOSI
|-
|Pin ALT-2J1.5||IO_L10P_T1_AD11P_35||FPGA.IO_L10P_T1_AD11P_35||K19||||||||KEY_ROW5
|-
|Pin ALT-3J1.7||IO_L11P_T1_SRCC_35||FPGA.IO_L11P_T1_SRCC_35||L16||||||||AUD4_RXC
|-
|Pin ALT-5J1.9||IO_L8N_T1_AD10N_35||FPGA.IO_L8N_T1_AD10N_35||M18||||||||GPIO1_IO11
|-
|rowspan="5"|J1.311|rowspan="5"|TBDIO_L7N_T1_AD2N_35|rowspan="5"|TBDFPGA.IO_L7N_T1_AD2N_35|rowspan="5"|TBDM20|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.13||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-2J1.15||IO_L9P_T1_DQS_AD3P_35||FPGA.IO_L9P_T1_DQS_AD3P_35||L19||||||||TBD
|-
|Pin ALT-3J1.17||IO_L9N_T1_DQS_AD3N_35||FPGA.IO_L9N_T1_DQS_AD3N_35||L20||||||||TBD
|-
|Pin ALT-5J1.19||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1.521|rowspan="5"|TBDIO_L20P_T3_AD6P_35|rowspan="5"|TBDFPGA.IO_L20P_T3_AD6P_35|rowspan="5"|TBDK14|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.23||IO_L20N_T3_AD6N_35||FPGA.IO_L20N_T3_AD6N_35||J14||||||||TBD
|-
|Pin ALT-2J1.25||IO_L22P_T3_AD7P_35||FPGA.IO_L22P_T3_AD7P_35||L14||||||||TBD
|-
|Pin ALT-3J1.27||IO_L12N_T1_MRCC_35||FPGA.IO_L12N_T1_MRCC_35||K18||||||||TBD
|-
|Pin ALT-5J1.29||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1.731|rowspan="5"|TBDIO_L21P_T3_DQS_AD14P_35|rowspan="5"|TBDFPGA.IO_L21P_T3_DQS_AD14P_35|rowspan="5"|TBDN15|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.33||IO_L21N_T3_DQS_AD14N_35||FPGA.IO_L21N_T3_DQS_AD14N_35||N16||||||||TBD
|-
|Pin ALT-2J1.35||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-3J1.37||IO_L17N_T2_AD5N_35||FPGA.IO_L17N_T2_AD5N_35||H20||||||||TBD
|-
|Pin ALT-5J1.39||IO_L13N_T2_MRCC_35||FPGA.IO_L13N_T2_MRCC_35||H17||||||||TBD
|-
|rowspan="5"|J1.941|rowspan="5"|TBDIO_L19P_T3_35|rowspan="5"|TBDFPGA.IO_L19P_T3_35|rowspan="5"|TBDH15|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.43||IO_L18P_T2_AD13P_35||FPGA.IO_L18P_T2_AD13P_35||G19||||||||TBD
|-
|Pin ALT-2J1.45||IO_L16P_T2_35||FPGA.IO_L16P_T2_35||G17||||||||TBD
|-
|Pin ALT-3J1.47||IO_L15N_T2_DQS_AD12N_35||FPGA.IO_L15N_T2_DQS_AD12N_35||F20||||||||TBD
|-
|Pin ALT-5J1.49||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1.1151|rowspan="5"|TBDIO_L2N_T0_AD8N_35|rowspan="5"|TBDFPGA.IO_L2N_T0_AD8N_35|rowspan="5"|TBDA20|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.53||IO_L1N_T0_AD0N_35||FPGA.IO_L1N_T0_AD0N_35||B20||||||||TBD
|-
|Pin ALT-2J1.55||IO_L5N_T0_AD9N_35||FPGA.IO_L5N_T0_AD9N_35||E19||||||||TBD
|-
|Pin ALT-3J1.57||IO_L5P_T0_AD9P_35||FPGA.IO_L5P_T0_AD9P_35||E18||||||||TBD
|-
|Pin ALT-5J1.59||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1.1361|rowspan="5"|TBDIO_L3P_T0_DQS_AD1P_35|rowspan="5"|TBDFPGA.IO_L3P_T0_DQS_AD1P_35|rowspan="5"|TBDE17|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.63||IO_L3N_T0_DQS_AD1N_35||FPGA.IO_L3N_T0_DQS_AD1N_35||D18||||||||TBD
|-
|Pin ALT-2J1.65||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-3J1.67||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||TBD
|-
|Pin ALT-5J1.69||XADC_AGND||FPGA.GNDADC_0||J10||||||||TBD
|-
|rowspan="5"|J1.1571|rowspan="5"|TBDXADC_AGND|rowspan="5"|TBDFPGA.GNDADC_0|rowspan="5"|TBDJ10|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.73||PS_MIO45_501 ||CPU.PS_MIO45_501||B15||||||||TBD
|-
|Pin ALT-2J1.75||PS_MIO44_501||CPU.PS_MIO44_501||F13||||||||TBD
|-
|Pin ALT-3J1.77||PS_MIO43_501||CPU.PS_MIO43_501||A9||||||||TBD
|-
|Pin ALT-5J1.79||PS_MIO42_501||CPU.PS_MIO42_501||E12||||||||TBD
|-
|rowspan="5"|J1.1781|rowspan="5"|TBDPS_MIO41_501|rowspan="5"|TBDCPU.PS_MIO41_501|rowspan="5"|TBDC17|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.83||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-2J1.85||PS_MIO40_501||CPU.PS_MIO40_501||D14||||||||TBD
|-
|Pin ALT-3J1.87||ETH_MDIO||CPU.PS_MIO53_501<br>LAN.MDIO||C11<br>37||||||||TBD
|-
|Pin ALT-5J1.89||ETH_MDC||CPU.PS_MIO12_501<br>LAN.MDC||C10<br>36||||||||TBD
|-
|rowspan="5"|J1.1991|rowspan="5"|TBDETH_LED1|rowspan="5"|TBDLAN.LED1 / PME_N1|rowspan="5"|TBD17|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.93||ETH_LED2||LAN.LED2||15||||||||TBD
|-
|Pin ALT-2J1.95||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-3J1.97||ETH_TXRX1_M||LAN.TXRXM_B||6||||||||TBD
|-
|Pin ALT-J1.99||ETH_TXRX1_P||LAN.TXRXP_B||5|TBD|||||||
|-
|rowspan="5"|J1.21101|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.103||ETH_TXRX0_M||LAN.TXRXM_A||3||||||||TBD
|-
|Pin ALT-J1.105||ETH_TXRX0_P||LAN.TXRXP_A||2|TBD|||||||
|-
|Pin ALT-3J1.107||DVDDH||LAN.DVDDH||16<br>34<br>40||||||||TBD
|-
|Pin ALT-5J1.109||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1.23111|rowspan="5"|TBDUSBOTG_CPEN|rowspan="5"|TBDUSB.CPEN|rowspan="5"|TBD7|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.113||OTG_VBUS||USB.OTG_VBUS||2||||||||TBD
|-
|Pin ALT-2J1.115||OTG_ID||USB.ID||1||||||||TBD
|-
|Pin ALT-3J1.117||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J1.119|TBD|SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500||A6|||||||| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|rowspan="5"|J1.25121|rowspan="5"|TBDSPI0_DQ2/MODE2/NAND_IO2|rowspan="5"|TBDCPU.PS_MIO4_500|rowspan="5"|TBDB7|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBDThis signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|Pin ALT-1J1.123|TBD|SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500||D6|||||||| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|Pin ALT-2J1.125|TBD|SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500||B8|||||||| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|Pin ALT-3J1.127||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J1.129|TBD|SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500||A5|||||||| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|rowspan="5"|J1.27131|rowspan="5"|TBDNAND_BUSY|rowspan="5"|TBDCPU.PS_MIO14_500|rowspan="5"|TBDC5|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-J1.133||PS_MIO15_500||CPU.PS_MIO15_500<br>WDT.WDI||C8<br>1|TBD|||||||See also [[Watchdog_(Bora)|this page]]
|-
|Pin ALT-2J1.135||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALTJ1.137||MEM_WPN||NAND.WP - NOR.WP/IO2||19 -3C4||||||||TBD
|-
|Pin ALT-5J1.139||DGND||DGND||n.a.||||||||TBD
|-
|rowspan} ==J1 even pins (2 to 140)== {| class="5wikitable"{|J1.29{{table}}|rowspanstyle="5background:#f0f0f0;" align="center"|TBD'''Pin'''|rowspanstyle="5background:#f0f0f0;" align="center"|TBD'''Pin Name'''|rowspanstyle="5background:#f0f0f0;" align="center"|TBD'''Internal Connections'''|rowspanstyle="background:#f0f0f0;" align="5center"|TBD'''Ball/pin #'''|rowspanstyle="background:#f0f0f0;" align="5center"|TBD'''Supply Group'''|rowspanstyle="background:#f0f0f0;" align="5center"|TBD'''Type'''|Pin ALT-0style="background:#f0f0f0;" align="center" |'''Voltage'''|TBDstyle="background:#f0f0f0;" align="center" |'''Note'''
|-
|Pin ALT-1J1.2||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||TBD
|-
|Pin ALT-2J1.4||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-3J1.6||IO_L10N_T1_AD11N_35||FPGA.IO_L10N_T1_AD11N_35||J19||||||||TBD
|-
|Pin ALT-5J1.8||IO_L12P_T1_MRCC_35||FPGA.IO_L12P_T1_MRCC_35||K17||||||||TBD
|-
|rowspan="5"|J1.3110|rowspan="5"|TBDIO_L11N_T1_SRCC_35|rowspan="5"|TBDFPGA.IO_L11N_T1_SRCC_35|rowspan="5"|TBDL17|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.12||IO_L8P_T1_AD10P_35||FPGA.IO_L8P_T1_AD10P_35||M17||||||||TBD
|-
|Pin ALT-2J1.14||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-3J1.16||IO_L24N_T3_AD15N_35||FPGA.IO_L24N_T3_AD15N_35||J16||||||||TBD
|-
|Pin ALT-5J1.18||IO_25_35||FPGA.IO_25_35||J15||||||||TBD
|-
|rowspan="5"|J1.3320|rowspan="5"|TBDIO_L24P_T3_AD15P_35|rowspan="5"|TBDFPGA.IO_L24P_T3_AD15P_35|rowspan="5"|TBDK16|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.22||IO_L23N_T3_35||FPGA.IO_L23N_T3_35||M15||||||||TBD
|-
|Pin ALT-2J1.24||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-3J1.26||IO_L22N_T3_AD7N_35||FPGA.IO_L22N_T3_AD7N_35||L15||||||||TBD
|-
|Pin ALT-5J1.28||IO_L23P_T3_35||FPGA.IO_L23P_T3_35||M14||||||||TBD
|-
|rowspan="5"|J1.3530|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.32||IO_L17P_T2_AD5P_35||FPGA.IO_L17P_T2_AD5P_35||J20||||||||TBD
|-
|Pin ALT-2J1.34||IO_L14P_T2_AD4P_SRCC_35||FPGA.IO_L14P_T2_AD4P_SRCC_35||J18||||||||TBD
|-
|Pin ALT-3J1.36||IO_L14N_T2_AD4N_SRCC_35||FPGA.IO_L14N_T2_AD4N_SRCC_35||H18||||||||TBD
|-
|Pin ALT-5J1.38||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1.3740|rowspan="5"|TBDIO_L13P_T2_MRCC_35|rowspan="5"|TBDFPGA.IO_L13P_T2_MRCC_35|rowspan="5"|TBDH16|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.42||IO_L18N_T2_AD13N_35||FPGA.IO_L18N_T2_AD13N_35||G20||||||||TBD
|-
|Pin ALT-2J1.44||IO_L16N_T2_35||FPGA.IO_L16N_T2_35||G18||||||||TBD
|-
|Pin ALT-3J1.46||IO_L15P_T2_DQS_AD12P_35||FPGA.IO_L15P_T2_DQS_AD12P_35||F19||||||||TBD
|-
|Pin ALT-5J1.48||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1.3950|rowspan="5"|TBDIO_L1P_T0_AD0P_35|rowspan="5"|TBDFPGA.IO_L1P_T0_AD0P_35|rowspan="5"|TBDC20|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.52||IO_L2P_T0_AD8P_35||FPGA.IO_L2P_T0_AD8P_35||B19||||||||TBD
|-
|Pin ALT-2J1.54||IO_L4N_T0_35||FPGA.IO_L4N_T0_35||D20||||||||TBD
|-
|Pin ALT-3J1.56||IO_L4P_T0_35||FPGA.IO_L4P_T0_35||D19||||||||TBD
|-
|Pin ALT-5J1.58||IO_L6P_T0_35||FPGA.IO_L6P_T0_35||F16||||||||TBD
|-
|rowspan="5"|J1.3160|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.62||IO_L6N_T0_VREF_35||FPGA.IO_L6N_T0_VREF_35||F17||||||||TBD
|-
|Pin ALT-2J1.64||IO_L19N_T3_VREF_35||FPGA.IO_L19N_T3_VREF_35||G15||||||||TBD
|-
|Pin ALT-3J1.66||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||TBD
|-
|Pin ALT-5J1.68||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||TBD
|-
|rowspan="5"|J1.3370|rowspan="5"|TBDXADC_AGND|rowspan="5"|TBDFPGA.GNDADC_0|rowspan="5"|TBDJ10|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.72||XADC_AGND||FPGA.GNDADC_0||J10||||||||TBD
|-
|Pin ALT-2J1.74||IO_0_35||FPGA.IO_0_35||G14||||||||TBD
|-
|Pin ALT-3J1.76||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J1.78||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1.3580|rowspan="5"|TBDPS_MIO49_501|rowspan="5"|TBDCPU.PS_MIO49_501|rowspan="5"|TBDC12|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.82||PS_MIO48_501||CPU.PS_MIO48_501||B12||||||||TBD
|-
|Pin ALT-2J1.84||PS_MIO47_501||CPU.PS_MIO47_501||B14||||||||TBD
|-
|Pin ALT-3J1.86||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J1.88||PS_MIO46_501||CPU.PS_MIO46_501||D16||||||||TBD
|-
|rowspan="5"|J1.3790|rowspan="5"|TBDETH_INTN|rowspan="5"|TBDLAN.INT_N / PME_N2|rowspan="5"|TBD38|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.92||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-2J1.94||ETH_TXRX3_M||LAN.TXRXM_D||11||||||||TBD
|-
|Pin ALT-3J1.96||ETH_TXRX3_P||LAN.TXRXP_D||10||||||||TBD
|-
|Pin ALT-5J1.98||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1.39100|rowspan="5"|TBDETH_TXRX2_M|rowspan="5"|TBDLAN.TXRXM_C|rowspan="5"|TBD8|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.102||ETH_TXRX2_P||LAN.TXRXP_C||7||||||||TBD
|-
|Pin ALT-2J1.104||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-3J1.106||CLK125_NDO||LAN.CLK125_NDO||41||||||||TBD
|-
|Pin ALT-5J1.108||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1.41110|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.112||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-2J1.114||USBP1||USB.DP||6||||||||TBD
|-
|Pin ALT-3J1.116||USBM1||USB.DM||5||||||||TBD
|-
|Pin ALT-5J1.118||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1.43120|rowspan="5"|TBDSPI0_CS0N|rowspan="5"|TBDCPU.PS_MIO1_500<br>NOR.CS#|rowspan="5"|TBDA7<br>C2|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.122||NAND_CS0/SPI0_CS1||CPU.PS_MIO0_500<br>NAND.~CE||E6<br>9||||||||TBD
|-
|Pin ALT-2J1.124||NAND_IO3||CPU.PS_MIO13_500<br>NAND.I/O3||E8<br>32||||||||TBD
|-
|Pin ALT-3J1.126||NAND_IO4||CPU.PS_MIO9_500<br>NAND.I/O4||B5<br>41||||||||TBD
|-
|Pin ALT-5J1.128||NAND_IO5||CPU.PS_MIO10_500<br>NAND.I/O5||E9<br>42||||||||TBD
|-
|rowspan="5"|J1.45130|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.132||NAND_IO6||CPU.PS_MIO11_500<br>NAND.I/O6||C6<br>43||||||||TBD
|-
|Pin ALT-2J1.134||NAND_IO7||CPU.PS_MIO12_500<br>NAND.I/O7||D9<br>44||||||||TBD
|-
|Pin ALT-3J1.136|TBD|NAND_RD_B/VCFG1||CPU.PS_MIO8_500<br>NAND.~RE||D5<br>8|||||||| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|Pin ALT-5J1.138|TBD|NAND_CLE/VCFG0||CPU.PS_MIO7_500<br>NAND.CLE||D8<br>16|||||||| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
|-
|rowspan="5"|J1.47140|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|} ==J2 odd pins (1 to 139)== {| class="wikitable" {| {{table}}| style="background:#f0f0f0;" align="center" |'''Pin'''| style="background:#f0f0f0;" align="center" |'''Pin ALT-1Name'''| style="background:#f0f0f0;" align="center" |'''Internal Connections'''| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''| style="background:#f0f0f0;" align="center" |'''Supply Group'''| style="background:#f0f0f0;" align="center" |'''Type'''| style="background:#f0f0f0;" align="center" |'''Voltage'''|TBDstyle="background:#f0f0f0;" align="center" |'''Note'''
|-
|Pin ALT-2J2.1||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-J2.3|TBD|DGND||DGND||n.a.||||||||
|-
|Pin ALT-J2.5|TBD|IO_L8P_T1_34||FPGA.IO_L8P_T1_34||W14||||||||
|-
|rowspan="5"|J1J2.497|rowspan="5"|TBDIO_L8N_T1_34|rowspan="5"|TBDFPGA.IO_L8N_T1_34|rowspan="5"|TBDY14|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-J2.9||IO_L6P_T0_34||CAN.D<br>FPGA.IO_L6P_T0_34||1<br>P14||||||||TBD
|-
|Pin ALT-2J2.11||IO_L6N_T0_VREF_34||FPGA.IO_L6N_T0_VREF_34||R14||||||||TBD
|-
|Pin ALT-3J2.13||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J2.15||IO_L3P_T0_DQS_PUDC_B_34||FPGA.IO_L3P_T0_DQS_PUDC_B_34||U13|||||| Internally connected to 3V3 via 10K resistor ||TBD
|-
|rowspan="5"|J1J2.5117|rowspan="5"|TBDIO_L3N_T0_DQS_34|rowspan="5"|TBDFPGA.IO_L3N_T0_DQS_34|rowspan="5"|TBDV13|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.19||IO_L2P_T0_34||FPGA.IO_L2P_T0_34||T12||||||||TBD
|-
|Pin ALT-2J2.21||IO_L2N_T0_34||FPGA.IO_L2N_T0_34||U12||||||||TBD
|-
|Pin ALT-3J2.23||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J2.25||IO_L22P_T3_34||FPGA.IO_L22P_T3_34||W18||||||||TBD
|-
|rowspan="5"|J1J2.5327|rowspan="5"|TBDIO_L22N_T3_34|rowspan="5"|TBDFPGA.IO_L22N_T3_34|rowspan="5"|TBDW19|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.29||IO_L21P_T3_DQS_34||FPGA.IO_L21P_T3_DQS_34||V17||||||||TBD
|-
|Pin ALT-2J2.31||IO_L21N_T3_DQS_34||FPGA.IO_L21N_T3_DQS_34||V18||||||||TBD
|-
|Pin ALT-3J2.33||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J2.35||IO_L19P_T3_34||CAN.R<br>FPGA.IO_L19P_T3_34||4<br>R16||||||||TBD
|-
|rowspan="5"|J1J2.5537|rowspan="5"|TBDIO_L19N_T3_VREF_34|rowspan="5"|TBDFPGA.IO_L19N_T3_VREF_34|rowspan="5"|TBDR17|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.39||IO_L18P_T2_34||FPGA.IO_L18P_T2_34||V16||||||||TBD
|-
|Pin ALT-2J2.41||IO_L18N_T2_34||FPGA.IO_L18N_T2_34||W16||||||||TBD
|-
|Pin ALT-3J2.43||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J2.45||IO_L15P_T2_DQS_34||FPGA.IO_L15P_T2_DQS_34||T20||||||||TBD
|-
|rowspan="5"|J1J2.5747|rowspan="5"|TBDIO_L15N_T2_DQS_34|rowspan="5"|TBDFPGA.IO_L15N_T2_DQS_34|rowspan="5"|TBDU20|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.49||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-2J2.51||IO_L13P_T1_MRCC_34||FPGA.IO_L13P_T1_MRCC_34||N18||||||||TBD
|-
|Pin ALT-3J2.53||IO_L13N_T1_MRCC_34||FPGA.IO_L13N_T1_MRCC_34||P19||||||||TBD
|-
|Pin ALT-5J2.55||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1J2.5957|rowspan="5"|TBDIO_L11P_T1_SRCC_34|rowspan="5"|TBDFPGA.IO_L11P_T1_SRCC_34|rowspan="5"|TBDU14|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.59||IO_L11N_T1_SRCC_34||FPGA.IO_L11N_T1_SRCC_34||U15||||||||TBD
|-
|Pin ALT-2J2.61||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-3J2.63||IO_L10P_T1_34||FPGA.IO_L10P_T1_34||V15||||||||TBD
|-
|Pin ALT-5J2.65||IO_L10N_T1_34||FPGA.IO_L10N_T1_34||W15||||||||TBD
|-
|rowspan="5"|J1J2.6167|rowspan="5"|TBDIO_25_34|rowspan="5"|TBDFPGA.IO_25_34|rowspan="5"|TBDT19|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.69||IO_0_34||FPGA.IO_0_34||R19||||||||TBD
|-
|Pin ALT-2J2.71||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-3J2.73||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J2.75||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J2.6377|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.79||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J2.81||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J2.83||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J2.85||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J2.6587|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.89||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J2.91||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J2.93||RTC_32KHZ||RTC.32KHZ||1||||||||TBD
|-
|Pin ALT-5J2.95||RTC_RST||RTC.~RST ||4||||||||TBD
|-
|rowspan="5"|J1J2.6797|rowspan="5"|TBDXADC_VN_R|rowspan="5"|TBDFPGA.VN_0|rowspan="5"|TBDL10|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.99||XADC_VP_R||FPGA.VP_0||K9||||||||TBD
|-
|Pin ALT-2J2.101||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J2.103||CONN_SPI_RSTn||NOR.~RESET/RFU ||A4||||||||TBD
|-
|Pin ALT-5J2.105||CAN_L||CAN.L||6||||||||TBD
|-
|rowspan="5"|J1J2.69107|rowspan="5"|TBDCAN_H|rowspan="5"|TBDCAN.H|rowspan="5"|TBD7|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.109||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALTJ2.111||RTC_INT/SQW||RTC.RTC_INT/SQW||3|||||||| It can be left open if not used. When used, a proper pull-2|TBDup resistor is required on the carrier board. For further details, please refer to the Maxim Integrated DS3232 datasheet.
|-
|Pin ALT-3J2.113||RTC_VBAT||RTC.VBAT||6||||||||TBD
|-
|Pin ALTJ2.115||VBAT||CPU.VCCBATT_0||F11|| || || ||This pin is connected to the VCCBATT_0 (for the battery-backed RAM -5|TBDBBRAM) pin of the Zynq SOC. For additional information, please refer to the Zynq datasheet and TRM.
|-
|rowspan="5"|J1J2.71117|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.119||3.3VIN||+3.3 V||n.a.||||||||TBD
|-
|Pin ALT-2J2.121||3.3VIN||+3.3 V||n.a.||||||||TBD
|-
|Pin ALT-J2.123||3.3VIN||+3.3V||n.a.||||||||TBD
|-
|Pin ALT-5J2.125||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1J2.73127|rowspan="5"|TBD3.3VIN|rowspan="5"|TBD+3.3 V|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.129||3.3VIN||+3.3 V||n.a.||||||||TBD
|-
|Pin ALT-2J2.131||3.3VIN||+3.3 V||n.a.||||||||TBD
|-
|Pin ALT-J2.133||3.3VIN||+3.3V||n.a.||||||||TBD
|-
|Pin ALT-5J2.135||3.3VIN||+3.3 V||n.a.||||||||TBD
|-
|rowspan="5"|J1J2.75137|rowspan="5"|TBD3.3VIN|rowspan="5"|TBD+3.3 V|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.139||DGND||DGND||n.a.||||||||TBD
|-
|} ==J2 even pins (2 to 140)== {| class="wikitable" {| {{table}}| style="background:#f0f0f0;" align="center" |'''Pin'''| style="background:#f0f0f0;" align="center" |'''Pin ALT-2Name'''| style="background:#f0f0f0;" align="center" |'''Internal Connections'''| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''| style="background:#f0f0f0;" align="center" |'''Supply Group'''| style="background:#f0f0f0;" align="center" |'''Type'''| style="background:#f0f0f0;" align="center" |'''Voltage'''|TBDstyle="background:#f0f0f0;" align="center" |'''Note'''
|-
|Pin ALT-3J2.2||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J2.4||IO_L9P_T1_DQS_34||FPGA.IO_L9P_T1_DQS_34||T16||||||||TBD
|-
|rowspan="5"|J1J2.776|rowspan="5"|TBDIO_L9N_T1_DQS_34|rowspan="5"|TBDFPGA.IO_L9N_T1_DQS_34|rowspan="5"|TBDU17|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.8||IO_L7P_T1_34||FPGA.IO_L7P_T1_34||Y16||||||||TBD
|-
|Pin ALT-2J2.10||IO_L7N_T1_34||FPGA.IO_L7N_T1_34||Y17||||||||TBD
|-
|Pin ALT-3J2.12||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J2.14||IO_L5P_T0_34||FPGA.IO_L5P_T0_34||T14||||||||TBD
|-
|rowspan="5"|J1J2.7916|rowspan="5"|TBDIO_L5N_T0_34|rowspan="5"|TBDFPGA.IO_L5N_T0_34|rowspan="5"|TBDT15|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.18||IO_L4P_T0_34||FPGA.IO_L4P_T0_34||V12||||||||TBD
|-
|Pin ALT-2J2.20||IO_L4N_T0_34||FPGA.IO_L4N_T0_34||W13||||||||TBD
|-
|Pin ALT-3J2.22||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J2.24||IO_L24P_T3_34||FPGA.IO_L24P_T3_34||P15||||||||TBD
|-
|rowspan="5"|J1J2.8126|rowspan="5"|TBDIO_L24N_T3_34|rowspan="5"|TBDFPGA.IO_L24N_T3_34|rowspan="5"|TBDP16|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.28||IO_L23P_T3_34||FPGA.IO_L23P_T3_34||N17||||||||TBD
|-
|Pin ALT-2J2.30||IO_L23N_T3_34||FPGA.IO_L23N_T3_34||P18||||||||TBD
|-
|Pin ALT-3J2.32||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J2.34||IO_L20P_T3_34||FPGA.IO_L20P_T3_34||T17||||||||TBD
|-
|rowspan="5"|J1J2.8336|rowspan="5"|TBDIO_L20N_T3_34|rowspan="5"|TBDFPGA.IO_L20N_T3_34|rowspan="5"|TBDR18|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.38||IO_L1P_T0_34||FPGA.IO_L1P_T0_34||T11||||||||TBD
|-
|Pin ALT-2J2.40||IO_L1N_T0_34||FPGA.IO_L1N_T0_34||T10||||||||TBD
|-
|Pin ALT-3J2.42||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J2.44||IO_L17P_T2_34||FPGA.IO_L17P_T2_34||Y18||||||||TBD
|-
|rowspan="5"|J1J2.8546|rowspan="5"|TBDIO_L17N_T2_34|rowspan="5"|TBDFPGA.IO_L17N_T2_34|rowspan="5"|TBDY19|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.48||IO_L16P_T2_34||FPGA.IO_L16P_T2_34||V20||||||||TBD
|-
|Pin ALT-2J2.50||IO_L16N_T2_34||FPGA.IO_L16N_T2_34||W20||||||||TBD
|-
|Pin ALT-3J2.52||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J2.54||IO_L14P_T2_SRCC_34||FPGA.IO_L14P_T2_SRCC_34||N20||||||||TBD
|-
|rowspan="5"|J1J2.8756|rowspan="5"|TBDIO_L14N_T2_SRCC_34|rowspan="5"|TBDFPGA.IO_L14N_T2_SRCC_34|rowspan="5"|TBDP20|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.58||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-2J2.60||IO_L12P_T1_MRCC_34||FPGA.IO_L12P_T1_MRCC_34||U18||||||||TBD
|-
|Pin ALT-3J2.62||IO_L12N_T1_MRCC_34||FPGA.IO_L12N_T1_MRCC_34||U19||||||||TBD
|-
|Pin ALT-5J2.64||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1J2.8966|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.68||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J2.70||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J2.72||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J2.74||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J2.9176|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.78||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J2.80||JTAG_TDO||CPU.TDO_0||F6||||||||TBD
|-
|Pin ALT-3J2.82||JTAG_TDI||CPU.TDI_0||G6||||||||TBD
|-
|Pin ALT-5J2.84||JTAG_TMS||CPU.TMS_0||J6||||||||TBD
|-
|rowspan="5"|J1J2.9386|rowspan="5"|TBDJTAG_TCK|rowspan="5"|TBDCPU.TCK_0|rowspan="5"|TBDF9|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.88||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-2J2.90|TBD|FPGA_INIT_B||FPGA.INIT_B_0||R10||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]
|-
|Pin ALTJ2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||L6||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]] (10 kΩ pull-3|TBDup resistor is already mounted on BORA module)
|-
|Pin ALT-5J2.94|TBD|FPGA_DONE||FPGA.DONE_0||R11||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]
|-
|rowspan="5"|J1J2.9596|rowspan="5"|TBDWD_SET2|rowspan="5"|TBDWDT.SET2|rowspan="5"|TBD6|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.98||WD_SET1||WDT.SET1||5||||||||TBD
|-
|Pin ALT-2J2.100||WD_SET0||WDT.SET0||4||||||||TBD
|-
|Pin ALT-3J2.102||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J2.104|TBD|PS_MIO50_501||CPU.PS_MIO50_501<br>USBOTG.RESETB||B13<br>22|||||||| For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(Bora)#PS_MIO50_501]]
|-
|rowspan="5"J2.106|J1.97|rowspan="5"PS_MIO51_501|TBD|rowspan="5"CPU.PS_MIO51_501<br>ETHPHY1GB.RESET_N|TBD|rowspan="5"B9<br>42|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO51_501_.28J2.106.29 |TBDReset_scheme_(Bora)#PS_MIO51_501]]
|-
|Pin ALT-1J2.108||BOARD_PGOOD||PSUSWITCHFPGABANK13.ON<br>PSUSWITCHFPGABANK35.ON<br>PSUSWITCHFPGABANK500/34.ON<br>PSUSWITCHFPGABANK501.ON<br>DDRVREFREGULATOR.PGOOD||3<br>3<br>3<br>3<br>9||||||||TBD
|-
|Pin ALT-2J2.110||CB_PWR_GOOD ||1V0REGULATOR.ENABLE ||n.a.||||||||TBD
|-
|Pin ALT-3J2.112||SYS_RSTN||CPU.PS_SRST_B_501<br>MTR.~RST||B10<br>5||||||||TBD
|-
|Pin ALT-5J2.114||PORSTN||CPU.PS_POR_B_500||C7||||||||TBD
|-
|rowspan="5"|J1J2.99116|rowspan="5"|TBDMRSTN|rowspan="5"|TBDMTR.MR|rowspan="5"|TBD6|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.118||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-2J2.120||3.3VIN||+3.3 V||n.a.||||||||TBD
|-
|Pin ALT-J2.122||3.3VIN||+3.3V||n.a.||||||||TBD
|-
|Pin ALT-5J2.124||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1J2.101126|rowspan="5"|TBD3.3VIN|rowspan="5"|TBD+3.3 V|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.128||3.3VIN||+3.3 V||n.a.||||||||TBD
|-
|Pin ALT-2J2.130||3.3VIN||+3.3 V||n.a.||||||||TBD
|-
|Pin ALT-J2.132||3.3VIN||+3.3V||n.a.||||||||TBD
|-
|Pin ALT-5J2.134||3.3VIN||+3.3 V||n.a.||||||||TBD
|-
|rowspan="5"|J1J2.103136|rowspan="5"|TBD3.3VIN|rowspan="5"|TBD+3.3 V|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J2.138||3.3VIN||+3.3 V||n.a.||||||||TBD
|-
|Pin ALT-2J2.140||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.105|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.107|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD}|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-J3 odd pins (1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.109|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.111|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.113|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.115|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.117|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.119|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.121|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.123|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.125|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.127|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.129|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.131|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.133|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.135|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.137|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.to 139|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.141|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.143|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.145|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.147|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.149|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.151|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.153|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.155|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.157|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.159|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.161|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.163|rowspan)="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD{|rowspanclass="5wikitable"{|TBD{{table}}|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.165|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|'''Pin ALT-5|TBD|-|rowspan="5"|J1.167|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD'''|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|'''Pin ALT-3Name'''|TBD|-|Pin ALT-5|TBD|-|rowspanstyle="5background:#f0f0f0;"|J1.169|rowspanalign="5center"|TBD'''Internal Connections'''|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD'''Ball/pin #'''|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD'''Supply Group'''|rowspanstyle="5background:#f0f0f0;"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspanalign="5center"|J1.171'''Type'''|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD'''Voltage'''|rowspanstyle="5background:#f0f0f0;"|TBD|rowspan="5"|TBD|rowspanalign="5center"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD'''Note'''
|-
|Pin ALT-J3.1|TBD|N.C.||Not Connected||n.a.||||||||
|-
|Pin ALT-2J3.3||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.5||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.7||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.1739|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.11||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.13||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.15||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.17||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.17519|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.21||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.23||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.25||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.27||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.17729|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.31||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.33||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.35||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.37||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.17939|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.41||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.43||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.45||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.47||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.18149|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.51||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.53||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.55||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.57||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.18359|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.61||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.63||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.65||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.67||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.18569|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.71||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.73||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.75||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.77||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.18779|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.81||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.83||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.85||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.87||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.18989|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.91||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.93||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-3J3.95|TBD|VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|Pin ALT-5J3.97|TBD|VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|rowspan="5"|J1J3.19199|rowspan="5"|TBDVDDIO_BANK13|rowspan="5"|TBDFPGA.VCCO_13|rowspan="5"|TBDT8<br>U11<br>W7<br>Y10|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBDN.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|Pin ALT-1J3.101||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-2J3.103||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-3J3.105|TBD|IO_L21P_T3_DQS_13||FPGA.IO_L21P_T3_DQS_13||V11|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-5J3.107|TBD|IO_L21N_T3_DQS_13||FPGA.IO_L21N_T3_DQS_13||V10|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|rowspan="5"|J1J3.193109|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.111|TBD|IO_L19P_T3_13||FPGA.IO_L19P_T3_13||T5|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-2J3.113|TBD|IO_L19N_T3_VREF_13||FPGA.IO_L19N_T3_VREF_13||U5|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-3J3.115||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J3.117|TBD|IO_L18P_T2_13||FPGA.IO_L18P_T2_13||W11|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|rowspan="5"|J1J3.195119|rowspan="5"|TBDIO_L18N_T2_13|rowspan="5"|TBDFPGA.IO_L18N_T2_13|rowspan="5"|TBDY11|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBDNot available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-1J3.121||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-2J3.123|TBD|IO_L16P_T2_13||FPGA.IO_L16P_T2_13||W10|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-3J3.125|TBD|IO_L16N_T2_13||FPGA.IO_L16N_T2_13||W9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-5J3.127||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.197129|rowspan="5"|TBDIO_L14P_T2_SRCC_13|rowspan="5"|TBDFPGA.IO_L14P_T2_SRCC_13|rowspan="5"|TBDY9|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBDNot available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-1J3.131|TBD|IO_L14N_T2_SRCC_13||FPGA.IO_L14N_T2_SRCC_13||Y8|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-2J3.133||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-3J3.135|TBD|IO_L12P_T1_MRCC_13||FPGA.IO_L12P_T1_MRCC_13||T9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-5J3.137|TBD|IO_L12N_T1_MRCC_13||FPGA.IO_L12N_T1_MRCC_13||U10|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|rowspan="5"|J1J3.199|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-139|Pin ALT-2|TBDDGND|-|Pin ALT-3DGND|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1n.201|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1a.203|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD
|-
|}
==Pinout Table EVEN J3 even pins declaration (2 to 140)==
{| class="wikitable" ! latexfontsize="scriptsize"| Pin ! latexfontsize="scriptsize"{| Pin Name{{table}}! latexfontsize="scriptsize"| Internal Connections ! latexfontsizestyle="scriptsize"| Ball/pin background:# ! latexfontsize="scriptsizef0f0f0;"| Voltage domain! latexfontsizealign="scriptsizecenter"| Type '''Pin'''! latexfontsize="scriptsize"| Notes! colspanstyle="2background:#f0f0f0;" latexfontsizealign="scriptsizecenter"| Alternative Functions'''Pin Name'''|-|rowspanstyle="5background:#f0f0f0;"|J1.1|rowspanalign="5center"|SD2_CMD'''Internal Connections'''|rowspanstyle="5background:#f0f0f0;"|CPU.SD2_CMD|rowspanalign="5center"|F19'''Ball/pin #'''|rowspanstyle="5background:#f0f0f0;"|AXEL_IO_3V3|rowspanalign="5center"|IO'''Supply Group'''|rowspanstyle="5"|Notes|Pin ALT-0|SD2_CMD|-|Pin ALT-1|ECSPI5_MOSI|-|Pin ALT-2|KEY_ROW5|-|Pin ALT-3|AUD4_RXC|-|Pin ALT-5|GPIO1_IO11|-|rowspan="5background:#f0f0f0;"|J1.3|rowspanalign="5center"|TBD'''Type'''|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD'''Voltage'''|rowspanstyle="5background:#f0f0f0;"|TBD|rowspanalign="5center"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD'''Note'''
|-
|Pin ALT-3J3.2||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.4||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.56|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.8||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.10||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.12||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.14||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.716|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.18||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.20||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.22||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.24||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.926|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.28||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.30||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.32||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.34||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.1136|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.38||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.40||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.42||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.44||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.1346|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.48||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.50||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.52||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.54||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.1556|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.58||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-2J3.60||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.62||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-5J3.64||N.C.||Not Connected||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.1766|rowspan="5"|TBDN.C.|rowspan="5"|TBDNot Connected|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.68||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-2J3.70||N.C.||Not Connected||n.a.||||||||TBD
|-
|Pin ALT-3J3.72|TBD|MON_VCCPLL||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALT-5J3.74|TBD|MON_XADC_VCC||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|rowspan="5"|J1J3.1976|rowspan="5"|TBDMON_FPGA_VDDIO_BANK35|rowspan="5"|TBDn.a.|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBDBy default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALT-1J3.78|TBD|MON_FPGA_VDDIO_BANK34||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALT-2J3.80|TBD|MON_FPGA_VDDIO_BANK13||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALT-3J3.82|TBD|MON_1.8V_IO||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALT-5J3.84|TBD|MON_3.3V||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|rowspan="5"|J1J3.2186|rowspan="5"|TBDMON_1V2_ETH|rowspan="5"|TBDn.a.|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBDBy default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALT-1J3.88|TBD|MON_VDDQ_1V5||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALT-2J3.90|TBD|MON_1.8V||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALT-3J3.92|TBD|MON_1.0V||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
|Pin ALT-5J3.94||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.2396|rowspan="5"|TBDVDDIO_BANK13|rowspan="5"|TBDFPGA.VCCO_13|rowspan="5"|TBDT8<br>U11<br>W7<br>Y10|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBDN.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|Pin ALT-1J3.98|TBD|VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
|-
|Pin ALT-2J3.100|TBD|IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||V5|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-3J3.102||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J3.104|TBD|IO_L22P_T3_13||FPGA.IO_L22P_T3_13||V6|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|rowspan="5"|J1J3.25106|rowspan="5"|TBDIO_L22N_T3_13|rowspan="5"|TBDFPGA.IO_L22N_T3_13|rowspan="5"|TBDW6|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBDNot available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-1J3.108||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-2J3.110|TBD|IO_L20P_T3_13||FPGA.IO_L20P_T3_13||Y12|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-3J3.112|TBD|IO_L20N_T3_13||FPGA.IO_L20N_T3_13||Y13|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-5J3.114||DGND||DGND||n.a.||||||||TBD
|-
|rowspan="5"|J1J3.27116|rowspan="5"|TBDIO_L17P_T2_13|rowspan="5"|TBDFPGA.IO_L17P_T2_13|rowspan="5"|TBDU9|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBDNot available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-1J3.118|TBD|IO_L17N_T2_13||FPGA.IO_L17N_T2_13||U8|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-2J3.120||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-3J3.122|TBD|IO_L15P_T2_DQS_13||FPGA.IO_L15P_T2_DQS_13||V8|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-5J3.124|TBD|IO_L15N_T2_DQS_13||FPGA.IO_L15N_T2_DQS_13||W8|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|rowspan="5"|J1J3.29126|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBDn.a.|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J3.128|TBD|IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y7|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-2J3.130|TBD|IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y6|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-3J3.132||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-5J3.134|TBD|IO_L11P_T1_SRCC_13||FPGA.IO_L11P_T1_SRCC_13||U7|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|rowspan="5"|J1J3.31136|rowspan="5"|TBDIO_L11N_T1_SRCC_13|rowspan="5"|TBDFPGA.IO_L11N_T1_SRCC_13|rowspan="5"|TBDV7|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBDNot available on Bora SOMs equipped with the XC7Z010 SOC
|-
|Pin ALT-1J3.138||DGND||DGND||n.a.||||||||TBD
|-
|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.33|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.35|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.37|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.39|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.31|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.33|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.35|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.37|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.39|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.41|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.43|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.45|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.47|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.49|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.51|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.53|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.55|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.57|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.59|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.61|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.63|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.65|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.67|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.69|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.71|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.73|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.75|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.77|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.79|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.81|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.83|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.85|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.87|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.89|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.91|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.93|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.95|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.97|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.99|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.101|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.103|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.105|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.107|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.109|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.111|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.113|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.115|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.117|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.119|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.121|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.123|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.125|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.127|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.129|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.131|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.133|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.135|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.137|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.139|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.141|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.143|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.145|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.147|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.149|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.151|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.153|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.155|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.157|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.159|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.161|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.163|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.165|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.167|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.169|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.171|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.173|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.175|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.177|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.179|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.181|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.183|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.185|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.187|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.189|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.191|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.193|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.195|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.197|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1J3.199140|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1n.201|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1a.203|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD
|-
|}
 
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[[Category:BORA]]
U0007
Bureaucrats, dave_user, Administrators
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