Changes

Pinout (Bora)

18,413 bytes added, 07:44, 30 July 2021

Replaced content with "{{subst:Pinout | nome-som=BORA | kit-code=BELK}}"

<section begin=History/>{~~{InfoBoxTop}~~| style="border-collapse:collapse; "!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History|- !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|X.Y.Z|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD|-|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|[TBD_link X.Y.Z]|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|-|}<section end=History/><section begin=Body/>''TBD: modificare la tabella seguente con le caratteristiche dei pin del SOM'' ''TBD: modificare le due tabelle ODD e EVEN con la mappa completa dei pins'' '''TBD: nella tabella naming conventions, inserire il codice dei vari IC presenti (PMIC, PHY ETH, ecc.)''' ==Connectors and Pinout Table== === Connectors description ===In the following table are described all available connectors integrated on [[BORA]]:{~~{Applies To Bora}~~| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM DDR3 edge connector 204 pin||TE Connectivity 2-2013289-1|-|Jxx|TBD|TBD|TBD|-|Jxx|TBD|TBD|TBD|-|Jxx|TBD|TBD|TBD|-|Jxx|TBD|TBD|TBD|}~~{{InfoBoxBottom}}~~The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA pinout specifications. See the images below for reference: [[File:BORA-top.png|500px|thumb|BORA TOP view|none]][[File:BORA-bottom.png|500px|thumb|BORA BOTTOM view|none]] ===Pinout table naming conventions === This chapter contains the pinout description of the BORA module, grouped in two tables (odd and even pins) that report the pin mapping of the ''TBD: connector type'' BORA connector.

~~==Pinout table==~~

This chapter contains the pinout description of the Bora module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Bora connectors.

Each row in the pinout tables contains the following information:

* {|class="wikitable" style="width:50%;"|-|'''Pin~~: reference~~ '''| Reference to the connector pin* |-|'''Pin Name~~: pin~~ ''' | Pin (signal) name on the ~~Bora~~ BORA connectors* |-|'''Internal connections~~: connections~~ ''' | Connections to the ~~Bora~~ BORA components** CPU.<x> : pin connected to CPU ~~(processing system)~~ pad named <x>** FPGACAN.<x>: pin connected to ~~FPGA~~ the CAN transceiver (~~programmable logic~~''manufacturer'' ''part number'') ~~pad named <x>~~** CANPMIC.<x> : pin connected to the ~~CAN transceiver~~Power Manager IC (''manufacturer'' ''part number'')** LAN.<x> : pin connected to the LAN PHY(''manufacturer'' ''part number'')** USB.<x> : pin connected to the USB transceiver** NAND.<x>: pin connected to the flash NAND** NOR.<x>: pin connected to the flash NOR** SV.<x>: pin connected to voltage supervisor** MTR: pin connected to voltage monitors* |-|'''Ball/pin #: ''' | Component ball/pin number connected to signal* Supply Group: Power Supply Group|-|'''Voltage''' || I/O voltage levels |-* |'''Type''' | Pin type: ~~pin type~~** I = Input** O = Output** D = Differential** Z = High impedance** S = Power supply voltage** G = Ground** A = Analog signal|-|'''Notes'''|Remarks on special pin characteristics|-|'''Pin MUX alternative functions'''|Muxes:* Pin ALT-0* ~~Voltage: I/O voltage levels~~...* Pin ALT-NThe number of functions depends on platform|-|}

==~~J1 odd~~ Pinout Table ODD pins ~~(1 to 139)~~declaration ==

{| class="wikitable" {! latexfontsize="scriptsize"| ~~{{table}}~~Pin ! latexfontsize="scriptsize"| Pin Name! latexfontsize="scriptsize"| ~~style~~Internal Connections ! latexfontsize="~~background:~~scriptsize"| Ball/pin #~~f0f0f0;~~! latexfontsize="scriptsize"| Voltage domain! latexfontsize="scriptsize"| Type ! latexfontsize="scriptsize"| Notes! colspan="2" latexfontsize="scriptsize"| Alternative Functions|-|rowspan="5"|J1.1|rowspan="5"|SD2_CMD|rowspan="5"|CPU.SD2_CMD|rowspan="5"|F19|rowspan="5"|AXEL_IO_3V3|rowspan="5"|IO|rowspan="5"|Notes|Pin ALT-0|SD2_CMD|-|Pin ALT-1|ECSPI5_MOSI|-|Pin ALT-2|KEY_ROW5|-|Pin ALT-3|AUD4_RXC|-|Pin ALT-5|GPIO1_IO11|-|rowspan="5"|J1.3|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.5|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.7|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.9|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.11|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.13|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.15|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.17|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.19|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.21|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.23|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.25|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.27|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.29|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.31|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.33|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.35|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.37|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.39|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.31|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.33|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.35|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.37|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.39|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan=" ~~align~~5"|TBD|rowspan="5"|TBD|rowspan="~~center~~5" |~~'''~~TBD|Pin~~'''~~ALT-0|TBD| ~~style~~-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="~~background:#f0f0f0;~~5"|J1.41|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.43|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.45|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.47|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.49|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.51|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.53|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.55|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.57|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5" ~~align~~|TBD|rowspan="~~center~~5" |~~'''~~TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ~~Name'''~~ALT-5|TBD|-|rowspan="5"|J1.59|rowspan="5"|TBD| ~~style~~rowspan="~~background:#f0f0f0;~~5" ~~align~~|TBD|rowspan="~~center~~5" |~~'''Internal Connections'''~~TBD| ~~style~~rowspan="~~background:#f0f0f0;~~5" ~~align~~|TBD|rowspan="~~center~~5" |~~'''Ball/pin #'''~~TBD| ~~style~~rowspan="~~background:#f0f0f0;~~5" ~~align~~|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="~~center~~5" |~~'''Supply Group'''~~J1.61| ~~style~~rowspan="~~background:#f0f0f0;~~5" ~~align~~|TBD|rowspan="~~center~~5" |~~'''Type'''~~TBD| ~~style~~rowspan="~~background:#f0f0f0;~~5" ~~align~~|TBD|rowspan="~~center~~5" |~~'''Voltage'''~~TBD| ~~style~~rowspan="~~background:#f0f0f0;~~5" ~~align~~|TBD|rowspan="~~center~~5" |~~'''Note'''~~TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD

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|~~J1.3||IO_L7P_T1_AD2P_35||FPGA.IO_L7P_T1_AD2P_35||M19|||||||~~Pin ALT-1|TBD

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|~~J1.5||IO_L10P_T1_AD11P_35||FPGA.IO_L10P_T1_AD11P_35||K19|||||||~~Pin ALT-2|TBD

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|~~J1.7||IO_L11P_T1_SRCC_35||FPGA.IO_L11P_T1_SRCC_35||L16|||||||~~Pin ALT-3|TBD

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|~~J1.9||IO_L8N_T1_AD10N_35||FPGA.IO_L8N_T1_AD10N_35||M18|||||||~~Pin ALT-5|TBD

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|~~J1.13||DGND||DGND||n.a.|||||||~~Pin ALT-1|TBD

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|~~J1.15||IO_L9P_T1_DQS_AD3P_35||FPGA.IO_L9P_T1_DQS_AD3P_35||L19|||||||~~Pin ALT-2|TBD

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|~~J1.17||IO_L9N_T1_DQS_AD3N_35||FPGA.IO_L9N_T1_DQS_AD3N_35||L20|||||||~~Pin ALT-3|TBD

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|~~J1.19||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

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|~~J1.23||IO_L20N_T3_AD6N_35||FPGA.IO_L20N_T3_AD6N_35||J14|||||||~~Pin ALT-1|TBD

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|~~J1.25||IO_L22P_T3_AD7P_35||FPGA.IO_L22P_T3_AD7P_35||L14|||||||~~Pin ALT-2|TBD

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|~~J1.27||IO_L12N_T1_MRCC_35||FPGA.IO_L12N_T1_MRCC_35||K18|||||||~~Pin ALT-3|TBD

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|~~J1.29||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

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|~~J1.33||IO_L21N_T3_DQS_AD14N_35||FPGA.IO_L21N_T3_DQS_AD14N_35||N16|||||||~~Pin ALT-1|TBD

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|~~J1.35||DGND||DGND||n.a.|||||||~~Pin ALT-2|TBD

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|~~J1.37||IO_L17N_T2_AD5N_35||FPGA.IO_L17N_T2_AD5N_35||H20|||||||~~Pin ALT-3|TBD

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|~~J1.39||IO_L13N_T2_MRCC_35||FPGA.IO_L13N_T2_MRCC_35||H17|||||||~~Pin ALT-5|TBD

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|~~J1.43||IO_L18P_T2_AD13P_35||FPGA.IO_L18P_T2_AD13P_35||G19|||||||~~Pin ALT-1|TBD

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|~~J1.45||IO_L16P_T2_35||FPGA.IO_L16P_T2_35||G17|||||||~~Pin ALT-2|TBD

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|~~J1.47||IO_L15N_T2_DQS_AD12N_35||FPGA.IO_L15N_T2_DQS_AD12N_35||F20|||||||~~Pin ALT-3|TBD

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|~~J1.49||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

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|~~J1.53||IO_L1N_T0_AD0N_35||FPGA.IO_L1N_T0_AD0N_35||B20|||||||~~Pin ALT-1|TBD

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|~~J1.55||IO_L5N_T0_AD9N_35||FPGA.IO_L5N_T0_AD9N_35||E19|||||||~~Pin ALT-2|TBD

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|~~J1.57||IO_L5P_T0_AD9P_35||FPGA.IO_L5P_T0_AD9P_35||E18|||||||~~Pin ALT-3|TBD

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|~~J1.59||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

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|~~J1.63||IO_L3N_T0_DQS_AD1N_35||FPGA.IO_L3N_T0_DQS_AD1N_35||D18|||||||~~Pin ALT-1|TBD

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|~~J1.65||DGND||DGND||n.a.|||||||~~Pin ALT-2|TBD

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|~~J1.67||VDDIO_BANK35||FPGA.VCCO_35||C19 F18 H14 J17 K20 M16|||||||~~Pin ALT-3|TBD

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|~~J1.69||XADC_AGND||FPGA.GNDADC_0||J10|||||||~~Pin ALT-5|TBD

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|~~J1.73||PS_MIO45_501 ||CPU.PS_MIO45_501||B15|||||||~~Pin ALT-1|TBD

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|~~J1.75||PS_MIO44_501||CPU.PS_MIO44_501||F13|||||||~~Pin ALT-2|TBD

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|~~J1.77||PS_MIO43_501||CPU.PS_MIO43_501||A9|||||||~~Pin ALT-3|TBD

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|~~J1.79||PS_MIO42_501||CPU.PS_MIO42_501||E12|||||||~~Pin ALT-5|TBD

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|~~J1.83||DGND||DGND||n.a.|||||||~~Pin ALT-1|TBD

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|~~J1.85||PS_MIO40_501||CPU.PS_MIO40_501||D14|||||||~~Pin ALT-2|TBD

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|~~J1.87||ETH_MDIO||CPU.PS_MIO53_501 LAN.MDIO||C11 37|||||||~~Pin ALT-3|TBD

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|~~J1.89||ETH_MDC||CPU.PS_MIO12_501 LAN.MDC||C10 36|||||||~~Pin ALT-5|TBD

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|~~J1.93||ETH_LED2||LAN.LED2||15|||||||~~Pin ALT-1|TBD

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|~~J1.95||DGND||DGND||n.a.|||||||~~Pin ALT-2|TBD

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|~~J1.97||ETH_TXRX1_M||LAN.TXRXM_B||6|||||||~~Pin ALT-3|TBD

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|~~J1.99||ETH_TXRX1_P||LAN.TXRXP_B||~~Pin ALT-5|~~|||||||~~TBD

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|~~J1.103||ETH_TXRX0_M||LAN.TXRXM_A||3|||||||~~Pin ALT-1|TBD

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|~~J1.105||ETH_TXRX0_P||LAN.TXRXP_A||~~Pin ALT-2|~~|||||||~~TBD

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|~~J1.107||DVDDH||LAN.DVDDH||16 34 40|||||||~~Pin ALT-3|TBD

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|~~J1.109||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J1.113||OTG_VBUS||USB.OTG_VBUS||2|||||||~~Pin ALT-1|TBD

|-

|~~J1.115||OTG_ID||USB.ID||1|||||||~~Pin ALT-2|TBD

|-

|~~J1.117||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J1.119~~Pin ALT-5|~~|SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500||A6|||||||| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)~~TBD

|-

|-

|~~J1.123~~Pin ALT-1|~~|SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500||D6|||||||| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)~~TBD

|-

|~~J1.125~~Pin ALT-2|~~|SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500||B8|||||||| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)~~TBD

|-

|~~J1.127||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J1.129~~Pin ALT-5|~~|SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500||A5|||||||| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)~~TBD

|-

|-

|~~J1.133||PS_MIO15_500||CPU.PS_MIO15_500 WDT.WDI||C8 ~~Pin ALT-1|~~|||||||See also [[Watchdog_(Bora)|this page]]~~TBD

|-

|~~J1.135||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J1.137||MEM_WPN||NAND.WP - NOR.WP/IO2||19~~ Pin ALT- ~~C4|||||||~~3|TBD

|-

|Pin ALT-5|TBD|-|rowspan="5"|J1.91|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.93|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.95|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.97|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.99|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.101|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.103|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.105|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.107|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.109|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.111|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.113|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.115|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.117|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.119|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.121|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.123|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.125|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.127|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.129|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.131|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.133|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.135|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.137|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.139|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.141|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.143|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.145|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.147|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.149|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.151|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.153|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.155|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.157|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.159|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.161|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|~~DGND~~-|Pin ALT-5|~~DGND~~TBD|-|nrowspan="5"|J1.a163|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.165|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.167|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.169|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.171|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.173|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.175|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.177|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.179|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.181|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.183|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.185|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.187|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.189|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.191|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.193|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.195|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.197|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.199|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.201|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.203|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD

|-

|}

==~~J1 even~~ Pinout Table EVEN pins ~~(2 to 140)~~declaration ==

{| class="wikitable" ~~{| {{table}}| style="background:#f0f0f0;" align~~! latexfontsize="~~center~~scriptsize" |~~'''~~Pin~~'''| style="background:#f0f0f0;" align~~! latexfontsize="~~center~~scriptsize" |~~'''~~Pin Name~~'''| style="background:#f0f0f0;" align~~! latexfontsize="~~center~~scriptsize" |~~'''~~Internal Connections~~'''| style="background:#f0f0f0;" align~~! latexfontsize="~~center~~scriptsize" |~~'''~~Ball/pin #~~'''| style="background:#f0f0f0;" align~~! latexfontsize="~~center~~scriptsize" |~~'''Supply Group'''~~Voltage domain~~| style="background:#f0f0f0;" align~~! latexfontsize="~~center~~scriptsize" |~~'''~~Type~~'''| style="background:#f0f0f0;" align~~! latexfontsize="~~center~~scriptsize" |~~'''Voltage'''~~Notes~~| style~~! colspan="~~background:#f0f0f0;~~2" ~~align~~latexfontsize="~~center~~scriptsize" |~~'''Note'''~~Alternative Functions

|-

|-

|~~J1.4||DGND||DGND||n.a.|||||||~~Pin ALT-1|ECSPI5_MOSI

|-

|~~J1.6||IO_L10N_T1_AD11N_35||FPGA.IO_L10N_T1_AD11N_35||J19|||||||~~Pin ALT-2|KEY_ROW5

|-

|~~J1.8||IO_L12P_T1_MRCC_35||FPGA.IO_L12P_T1_MRCC_35||K17|||||||~~Pin ALT-3|AUD4_RXC

|-

|~~J1.10||IO_L11N_T1_SRCC_35||FPGA.IO_L11N_T1_SRCC_35||L17|||||||~~Pin ALT-5|GPIO1_IO11

|-

|-

|~~J1.14||DGND||DGND||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J1.16||IO_L24N_T3_AD15N_35||FPGA.IO_L24N_T3_AD15N_35||J16|||||||~~Pin ALT-2|TBD

|-

|~~J1.18||IO_25_35||FPGA.IO_25_35||J15|||||||~~Pin ALT-3|TBD

|-

|~~J1.20||IO_L24P_T3_AD15P_35||FPGA.IO_L24P_T3_AD15P_35||K16|||||||~~Pin ALT-5|TBD

|-

|-

|~~J1.24||DGND||DGND||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J1.26||IO_L22N_T3_AD7N_35||FPGA.IO_L22N_T3_AD7N_35||L15|||||||~~Pin ALT-2|TBD

|-

|~~J1.28||IO_L23P_T3_35||FPGA.IO_L23P_T3_35||M14|||||||~~Pin ALT-3|TBD

|-

|~~J1.30||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J1.34||IO_L14P_T2_AD4P_SRCC_35||FPGA.IO_L14P_T2_AD4P_SRCC_35||J18|||||||~~Pin ALT-1|TBD

|-

|~~J1.36||IO_L14N_T2_AD4N_SRCC_35||FPGA.IO_L14N_T2_AD4N_SRCC_35||H18|||||||~~Pin ALT-2|TBD

|-

|~~J1.38||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J1.40||IO_L13P_T2_MRCC_35||FPGA.IO_L13P_T2_MRCC_35||H16|||||||~~Pin ALT-5|TBD

|-

|-

|~~J1.44||IO_L16N_T2_35||FPGA.IO_L16N_T2_35||G18|||||||~~Pin ALT-1|TBD

|-

|~~J1.46||IO_L15P_T2_DQS_AD12P_35||FPGA.IO_L15P_T2_DQS_AD12P_35||F19|||||||~~Pin ALT-2|TBD

|-

|~~J1.48||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J1.50||IO_L1P_T0_AD0P_35||FPGA.IO_L1P_T0_AD0P_35||C20|||||||~~Pin ALT-5|TBD

|-

|-

|~~J1.54||IO_L4N_T0_35||FPGA.IO_L4N_T0_35||D20|||||||~~Pin ALT-1|TBD

|-

|~~J1.56||IO_L4P_T0_35||FPGA.IO_L4P_T0_35||D19|||||||~~Pin ALT-2|TBD

|-

|~~J1.58||IO_L6P_T0_35||FPGA.IO_L6P_T0_35||F16|||||||~~Pin ALT-3|TBD

|-

|~~J1.60||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J1.64||IO_L19N_T3_VREF_35||FPGA.IO_L19N_T3_VREF_35||G15|||||||~~Pin ALT-1|TBD

|-

|~~J1.66||VDDIO_BANK35||FPGA.VCCO_35||C19 F18 H14 J17 K20 M16|||||||~~Pin ALT-2|TBD

|-

|~~J1.68||VDDIO_BANK35||FPGA.VCCO_35||C19 F18 H14 J17 K20 M16|||||||~~Pin ALT-3|TBD

|-

|~~J1.70||XADC_AGND||FPGA.GNDADC_0||J10|||||||~~Pin ALT-5|TBD

|-

|-

|~~J1.74||IO_0_35||FPGA.IO_0_35||G14|||||||~~Pin ALT-1|TBD

|-

|~~J1.76||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J1.78||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J1.80||PS_MIO49_501||CPU.PS_MIO49_501||C12|||||||~~Pin ALT-5|TBD

|-

|-

|~~J1.84||PS_MIO47_501||CPU.PS_MIO47_501||B14|||||||~~Pin ALT-1|TBD

|-

|~~J1.86||DGND||DGND||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J1.88||PS_MIO46_501||CPU.PS_MIO46_501||D16|||||||~~Pin ALT-3|TBD

|-

|~~J1.90||ETH_INTN||LAN.INT_N / PME_N2||38|||||||~~Pin ALT-5|TBD

|-

|-

|~~J1.94||ETH_TXRX3_M||LAN.TXRXM_D||11|||||||~~Pin ALT-1|TBD

|-

|~~J1.96||ETH_TXRX3_P||LAN.TXRXP_D||10|||||||~~Pin ALT-2|TBD

|-

|~~J1.98||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J1.100||ETH_TXRX2_M||LAN.TXRXM_C||8|||||||~~Pin ALT-5|TBD

|-

|-

|~~J1.104||DGND||DGND||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J1.106||CLK125_NDO||LAN.CLK125_NDO||41|||||||~~Pin ALT-2|TBD

|-

|~~J1.108||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J1.110||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J1.114||USBP1||USB.DP||6|||||||~~Pin ALT-1|TBD

|-

|~~J1.116||USBM1||USB.DM||5|||||||~~Pin ALT-2|TBD

|-

|~~J1.118||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J1.120||SPI0_CS0N||CPU.PS_MIO1_500 NOR.CS#||A7 C2|||||||~~Pin ALT-5|TBD

|-

|-

|~~J1.124||NAND_IO3||CPU.PS_MIO13_500 NAND.I/O3||E8 32|||||||~~Pin ALT-1|TBD

|-

|~~J1.126||NAND_IO4||CPU.PS_MIO9_500 NAND.I/O4||B5 41|||||||~~Pin ALT-2|TBD

|-

|~~J1.128||NAND_IO5||CPU.PS_MIO10_500 NAND.I/O5||E9 42|||||||~~Pin ALT-3|TBD

|-

|~~J1.130||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J1.134||NAND_IO7||CPU.PS_MIO12_500 NAND.I/O7||D9 44|||||||~~Pin ALT-1|TBD

|-

|~~J1.136~~Pin ALT-2|~~|NAND_RD_B/VCFG1||CPU.PS_MIO8_500 NAND.~RE||D5 8|||||||| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)~~TBD

|-

|~~J1.138~~Pin ALT-3|~~|NAND_CLE/VCFG0||CPU.PS_MIO7_500 NAND.CLE||D8 16|||||||| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)~~TBD

|-

|~~J1.140||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

|-

|}rowspan="5"|J1.29|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.31|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.33|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.35|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.37|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.39|rowspan="5"|TBD|rowspan="5"|TBD|rowspan=~~J2 odd pins (~~"5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1 ~~to 139)~~|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.31|rowspan="5"|TBD|rowspan="5"|TBD{| ~~class~~rowspan="~~wikitable~~5" {| ~~{{table}}~~TBD| ~~style~~rowspan="~~background:#f0f0f0;~~5" ~~align~~|TBD|rowspan="~~center~~5"|TBD|rowspan=" 5"|TBD|Pin ALT-0|TBD|-|~~'''~~Pin~~'''~~ALT-1| ~~style~~TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="~~background:#f0f0f0;~~5" ~~align~~|J1.33|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="~~center~~5" |~~'''~~TBD|rowspan="5"|TBD|Pin ~~Name'''~~ALT-0|TBD|-| ~~style~~Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="~~background:#f0f0f0;~~5" ~~align~~|J1.35|rowspan="~~center~~5" |~~'''Internal Connections'''~~TBD| ~~style~~rowspan="~~background:#f0f0f0;~~5" ~~align~~|TBD|rowspan="~~center~~5" |~~'''Ball/pin #'''~~TBD| ~~style~~rowspan="~~background:#f0f0f0;~~5" ~~align~~|TBD|rowspan="~~center~~5" |~~'''Supply Group'''~~TBD| ~~style~~rowspan="~~background:#f0f0f0;~~5" ~~align~~|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="~~center~~5" |~~'''Type'''~~J1.37| ~~style~~rowspan="~~background:#f0f0f0;~~5" ~~align~~|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="~~center~~5" |~~'''Voltage'''~~TBD| ~~style~~rowspan="~~background:#f0f0f0;~~5" ~~align~~|TBD|rowspan="~~center~~5" |~~'''Note'''~~TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.39|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.41|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.43|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.45|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.47|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.49|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.51|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.53|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.55|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.57|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.59|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.61|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.63|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.65|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.67|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.69|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.71|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.73|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.75|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.77|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.79|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.81|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.83|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.85|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.87|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.89|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.91|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD

|-

|~~J2.1||DGND||DGND||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J2.~~Pin ALT-3|~~|DGND||DGND||n.a.||||||||~~TBD

|-

|~~J2.~~Pin ALT-5|~~|IO_L8P_T1_34||FPGA.IO_L8P_T1_34||W14||||||||~~TBD

|-

|-

|~~J2.9||IO_L6P_T0_34||CAN.D FPGA.IO_L6P_T0_34||~~Pin ALT-1~~ P14|||||||~~|TBD

|-

|~~J2.11||IO_L6N_T0_VREF_34||FPGA.IO_L6N_T0_VREF_34||R14|||||||~~Pin ALT-2|TBD

|-

|~~J2.13||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J2.15||IO_L3P_T0_DQS_PUDC_B_34||FPGA.IO_L3P_T0_DQS_PUDC_B_34||U13|||||| Internally connected to 3V3 via 10K resistor |~~Pin ALT-5|TBD

|-

|-

|~~J2.19||IO_L2P_T0_34||FPGA.IO_L2P_T0_34||T12|||||||~~Pin ALT-1|TBD

|-

|~~J2.21||IO_L2N_T0_34||FPGA.IO_L2N_T0_34||U12|||||||~~Pin ALT-2|TBD

|-

|~~J2.23||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J2.25||IO_L22P_T3_34||FPGA.IO_L22P_T3_34||W18|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.29||IO_L21P_T3_DQS_34||FPGA.IO_L21P_T3_DQS_34||V17|||||||~~Pin ALT-1|TBD

|-

|~~J2.31||IO_L21N_T3_DQS_34||FPGA.IO_L21N_T3_DQS_34||V18|||||||~~Pin ALT-2|TBD

|-

|~~J2.33||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J2.35||IO_L19P_T3_34||CAN.R FPGA.IO_L19P_T3_34||4 R16|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.39||IO_L18P_T2_34||FPGA.IO_L18P_T2_34||V16|||||||~~Pin ALT-1|TBD

|-

|~~J2.41||IO_L18N_T2_34||FPGA.IO_L18N_T2_34||W16|||||||~~Pin ALT-2|TBD

|-

|~~J2.43||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J2.45||IO_L15P_T2_DQS_34||FPGA.IO_L15P_T2_DQS_34||T20|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.49||DGND||DGND||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J2.51||IO_L13P_T1_MRCC_34||FPGA.IO_L13P_T1_MRCC_34||N18|||||||~~Pin ALT-2|TBD

|-

|~~J2.53||IO_L13N_T1_MRCC_34||FPGA.IO_L13N_T1_MRCC_34||P19|||||||~~Pin ALT-3|TBD

|-

|~~J2.55||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.59||IO_L11N_T1_SRCC_34||FPGA.IO_L11N_T1_SRCC_34||U15|||||||~~Pin ALT-1|TBD

|-

|~~J2.61||DGND||DGND||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J2.63||IO_L10P_T1_34||FPGA.IO_L10P_T1_34||V15|||||||~~Pin ALT-3|TBD

|-

|~~J2.65||IO_L10N_T1_34||FPGA.IO_L10N_T1_34||W15|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.69||IO_0_34||FPGA.IO_0_34||R19|||||||~~Pin ALT-1|TBD

|-

|~~J2.71||DGND||DGND||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J2.73||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J2.75||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.79||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J2.81||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J2.83||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J2.85||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.89||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J2.91||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J2.93||RTC_32KHZ||RTC.32KHZ||1|||||||~~Pin ALT-3|TBD

|-

|~~J2.95||RTC_RST||RTC.~RST ||4|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.99||XADC_VP_R||FPGA.VP_0||K9|||||||~~Pin ALT-1|TBD

|-

|~~J2.101||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J2.103||CONN_SPI_RSTn||NOR.~RESET/RFU ||A4|||||||~~Pin ALT-3|TBD

|-

|~~J2.105||CAN_L||CAN.L||6|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.109||DGND||DGND||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J2.111||RTC_INT/SQW||RTC.RTC_INT/SQW||3~~Pin ALT-2|~~||||||| It can be left open if not used. When used, a proper pull-up resistor is required on the carrier board. For further details, please refer to the Maxim Integrated DS3232 datasheet.~~TBD

|-

|~~J2.113||RTC_VBAT||RTC.VBAT||6|||||||~~Pin ALT-3|TBD

|-

|~~J2.115||VBAT||CPU.VCCBATT_0||F11|| || || |~~Pin ALT-5|~~This pin is connected to the VCCBATT_0 (for the battery-backed RAM - BBRAM) pin of the Zynq SOC. For additional information, please refer to the Zynq datasheet and TRM.~~TBD

|-

|-

|~~J2.119||3.3VIN||+3.3 V||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J2.121||3.3VIN||+3.3 V||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J2.123||3.3VIN||+3.~~Pin ALT-3 ~~V||n.a.|||||||~~|TBD

|-

|~~J2.125||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.129||3.3VIN||+3.3 V||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J2.131||3.3VIN||+3.3 V||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J2.133||3.3VIN||+3.~~Pin ALT-3 ~~V||n.a.|||||||~~|TBD

|-

|~~J2.135||3.3VIN||+3.3 V||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.139||DGND||DGND||n.a.|||||||~~Pin ALT-1|TBD

|-

|} ~~==J2 even pins (~~Pin ALT-2 ~~to 140)==~~ ~~{| class="wikitable" {| {{table}}| style="background:#f0f0f0;" align="center" |'''Pin'''| style="background:#f0f0f0;" align="center" |'''Pin Name'''~~| ~~style="background:#f0f0f0;" align="center" |'''Internal Connections'''| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''| style="background:#f0f0f0;" align="center" |'''Supply Group'''| style="background:#f0f0f0;" align="center" |'''Type'''| style="background:#f0f0f0;" align="center" |'''Voltage'''| style="background:#f0f0f0;" align="center" |'''Note'''~~TBD

|-

|~~J2.2||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J2.4||IO_L9P_T1_DQS_34||FPGA.IO_L9P_T1_DQS_34||T16|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.8||IO_L7P_T1_34||FPGA.IO_L7P_T1_34||Y16|||||||~~Pin ALT-1|TBD

|-

|~~J2.10||IO_L7N_T1_34||FPGA.IO_L7N_T1_34||Y17|||||||~~Pin ALT-2|TBD

|-

|~~J2.12||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J2.14||IO_L5P_T0_34||FPGA.IO_L5P_T0_34||T14|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.18||IO_L4P_T0_34||FPGA.IO_L4P_T0_34||V12|||||||~~Pin ALT-1|TBD

|-

|~~J2.20||IO_L4N_T0_34||FPGA.IO_L4N_T0_34||W13|||||||~~Pin ALT-2|TBD

|-

|~~J2.22||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J2.24||IO_L24P_T3_34||FPGA.IO_L24P_T3_34||P15|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.28||IO_L23P_T3_34||FPGA.IO_L23P_T3_34||N17|||||||~~Pin ALT-1|TBD

|-

|~~J2.30||IO_L23N_T3_34||FPGA.IO_L23N_T3_34||P18|||||||~~Pin ALT-2|TBD

|-

|~~J2.32||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J2.34||IO_L20P_T3_34||FPGA.IO_L20P_T3_34||T17|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.38||IO_L1P_T0_34||FPGA.IO_L1P_T0_34||T11|||||||~~Pin ALT-1|TBD

|-

|~~J2.40||IO_L1N_T0_34||FPGA.IO_L1N_T0_34||T10|||||||~~Pin ALT-2|TBD

|-

|~~J2.42||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J2.44||IO_L17P_T2_34||FPGA.IO_L17P_T2_34||Y18|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.48||IO_L16P_T2_34||FPGA.IO_L16P_T2_34||V20|||||||~~Pin ALT-1|TBD

|-

|~~J2.50||IO_L16N_T2_34||FPGA.IO_L16N_T2_34||W20|||||||~~Pin ALT-2|TBD

|-

|~~J2.52||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J2.54||IO_L14P_T2_SRCC_34||FPGA.IO_L14P_T2_SRCC_34||N20|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.58||DGND||DGND||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J2.60||IO_L12P_T1_MRCC_34||FPGA.IO_L12P_T1_MRCC_34||U18|||||||~~Pin ALT-2|TBD

|-

|~~J2.62||IO_L12N_T1_MRCC_34||FPGA.IO_L12N_T1_MRCC_34||U19|||||||~~Pin ALT-3|TBD

|-

|~~J2.64||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.68||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J2.70||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J2.72||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J2.74||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.78||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J2.80||JTAG_TDO||CPU.TDO_0||F6|||||||~~Pin ALT-2|TBD

|-

|~~J2.82||JTAG_TDI||CPU.TDI_0||G6|||||||~~Pin ALT-3|TBD

|-

|~~J2.84||JTAG_TMS||CPU.TMS_0||J6|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.88||DGND||DGND||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J2.90~~Pin ALT-2|~~|FPGA_INIT_B||FPGA.INIT_B_0||R10||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]~~TBD

|-

|~~J2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0~~Pin ALT-3|~~|L6||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]~~ ~~(10 kΩ pull-up resistor is already mounted on BORA module)~~TBD

|-

|~~J2.94~~Pin ALT-5|~~|FPGA_DONE||FPGA.DONE_0||R11||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]~~TBD

|-

|-

|~~J2.98||WD_SET1||WDT.SET1||5|||||||~~Pin ALT-1|TBD

|-

|~~J2.100||WD_SET0||WDT.SET0||4|||||||~~Pin ALT-2|TBD

|-

|~~J2.102||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J2.104~~Pin ALT-5|~~|PS_MIO50_501||CPU.PS_MIO50_501 USBOTG.RESETB||B13 22|||||||| For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(Bora)#PS_MIO50_501]]~~TBD

|-

|J2rowspan="5"|J1.~~106|~~141|~~PS_MIO51_501~~rowspan="5"|TBD|~~CPU.PS_MIO51_501 ETHPHY1GB.RESET_N~~rowspan="5"|TBD|~~B9 42~~rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD| ~~For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO51_501_.28J2.106.29~~ Pin ALT-0| ~~Reset_scheme_(Bora)#PS_MIO51_501]]~~TBD

|-

|~~J2.108||BOARD_PGOOD||PSUSWITCHFPGABANK13.ON PSUSWITCHFPGABANK35.ON PSUSWITCHFPGABANK500/34.ON PSUSWITCHFPGABANK501.ON DDRVREFREGULATOR.PGOOD||3 3 3 3 9|||||||~~Pin ALT-1|TBD

|-

|~~J2.110||CB_PWR_GOOD ||1V0REGULATOR.ENABLE ||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J2.112||SYS_RSTN||CPU.PS_SRST_B_501 MTR.~RST||B10 5|||||||~~Pin ALT-3|TBD

|-

|~~J2.114||PORSTN||CPU.PS_POR_B_500||C7|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.118||DGND||DGND||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J2.120||3.3VIN||+3.3 V||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J2.122||3.3VIN||+3.~~Pin ALT-3 ~~V||n.a.|||||||~~|TBD

|-

|~~J2.124||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.128||3.3VIN||+3.3 V||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J2.130||3.3VIN||+3.3 V||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J2.132||3.3VIN||+3.~~Pin ALT-3 ~~V||n.a.|||||||~~|TBD

|-

|~~J2.134||3.3VIN||+3.3 V||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J2.138||3.3VIN||+3.3 V||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J2.140||DGND||DGND||n.a.|||||||~~Pin ALT-2|TBD

|-

|} ~~==J3 odd pins (1 to 139)==~~ ~~{| class="wikitable" {| {{table}}| style="background:#f0f0f0;" align="center" |'''~~Pin~~'''~~ALT-3| ~~style="background:#f0f0f0;" align="center" |'''Pin Name'''| style="background:#f0f0f0;" align="center" |'''Internal Connections'''| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''| style="background:#f0f0f0;" align="center" |'''Supply Group'''| style="background:#f0f0f0;" align="center" |'''Type'''| style="background:#f0f0f0;" align="center" |'''Voltage'''| style="background:#f0f0f0;" align="center" |'''Note'''~~TBD

|-

|~~J3.1||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.5||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.7||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.9||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.11||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.15||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.17||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.19||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.21||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.25||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.27||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.29||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.31||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.35||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.37||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.39||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.41||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.45||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.47||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.49||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.51||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.55||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.57||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.59||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.61||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.65||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.67||DGND||DGND||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.69||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.71||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.75||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.77||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.79||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.81||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.85||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.87||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.89||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.91||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.95~~Pin ALT-1||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].TBD

|-

|~~J3.97~~Pin ALT-2||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].TBD

|-

|~~J3.99~~Pin ALT-3||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].TBD

|-

|~~J3.101||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.105~~Pin ALT-1|~~|IO_L21P_T3_DQS_13||FPGA.IO_L21P_T3_DQS_13||V11|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.107~~Pin ALT-2|~~|IO_L21N_T3_DQS_13||FPGA.IO_L21N_T3_DQS_13||V10|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.109||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.111~~Pin ALT-5|~~|IO_L19P_T3_13||FPGA.IO_L19P_T3_13||T5|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|-

|~~J3.115||DGND||DGND||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.117~~Pin ALT-2|~~|IO_L18P_T2_13||FPGA.IO_L18P_T2_13||W11|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.119~~Pin ALT-3|~~|IO_L18N_T2_13||FPGA.IO_L18N_T2_13||Y11|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.121||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.125~~Pin ALT-1|~~|IO_L16N_T2_13||FPGA.IO_L16N_T2_13||W9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.127||DGND||DGND||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.129~~Pin ALT-3|~~|IO_L14P_T2_SRCC_13||FPGA.IO_L14P_T2_SRCC_13||Y9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.131~~Pin ALT-5|~~|IO_L14N_T2_SRCC_13||FPGA.IO_L14N_T2_SRCC_13||Y8|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|-

|~~J3.135~~Pin ALT-1|~~|IO_L12P_T1_MRCC_13||FPGA.IO_L12P_T1_MRCC_13||T9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.137~~Pin ALT-2|~~|IO_L12N_T1_MRCC_13||FPGA.IO_L12N_T1_MRCC_13||U10|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.139||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|} ~~==J3 even pins (2 to 140)==~~ ~~{| class="wikitable" {| {{table}}| style="background:#f0f0f0;" align="center" |'''~~Pin~~'''~~ALT-5| ~~style="background:#f0f0f0;" align="center" |'''Pin Name'''| style="background:#f0f0f0;" align="center" |'''Internal Connections'''| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''| style="background:#f0f0f0;" align="center" |'''Supply Group'''| style="background:#f0f0f0;" align="center" |'''Type'''| style="background:#f0f0f0;" align="center" |'''Voltage'''| style="background:#f0f0f0;" align="center" |'''Note'''~~TBD

|-

|-

|~~J3.4||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.6||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.8||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.10||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.14||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.16||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.18||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.20||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.24||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.26||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.28||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.30||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.34||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.36||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.38||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.40||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.44||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.46||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.48||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.50||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.54||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.56||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.58||N.C.||Not Connected||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.60||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.64||N.C.||Not Connected||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.66||N.C.||Not Connected||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.68||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.70||N.C.||Not Connected||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.74~~Pin ALT-1||MON_XADC_VCC||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.TBD

|-

|~~J3.76~~Pin ALT-2||MON_FPGA_VDDIO_BANK35||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.TBD

|-

|~~J3.78~~Pin ALT-3||MON_FPGA_VDDIO_BANK34||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.TBD

|-

|~~J3.80~~Pin ALT-5||MON_FPGA_VDDIO_BANK13||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.TBD

|-

|-

|~~J3.84~~Pin ALT-1||MON_3.3V||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.TBD

|-

|~~J3.86~~Pin ALT-2||MON_1V2_ETH||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.TBD

|-

|~~J3.88~~Pin ALT-3||MON_VDDQ_1V5||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.TBD

|-

|~~J3.90~~Pin ALT-5||MON_1.8V||n.a.||n.a.|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.TBD

|-

|-

|~~J3.94||DGND||DGND||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.96~~Pin ALT-2||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].TBD

|-

|~~J3.98~~Pin ALT-3||VDDIO_BANK13||FPGA.VCCO_13||T8 U11 W7 Y10|||||||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].TBD

|-

|~~J3.100~~Pin ALT-5|~~|IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||V5|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|-

|~~J3.104~~Pin ALT-1|~~|IO_L22P_T3_13||FPGA.IO_L22P_T3_13||V6|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.106~~Pin ALT-2|~~|IO_L22N_T3_13||FPGA.IO_L22N_T3_13||W6|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.108||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.110~~Pin ALT-5|~~|IO_L20P_T3_13||FPGA.IO_L20P_T3_13||Y12|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|-

|~~J3.114||DGND||DGND||n.a.|||||||~~Pin ALT-1|TBD

|-

|~~J3.116~~Pin ALT-2|~~|IO_L17P_T2_13||FPGA.IO_L17P_T2_13||U9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.118~~Pin ALT-3|~~|IO_L17N_T2_13||FPGA.IO_L17N_T2_13||U8|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.120||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

|-

|-

|~~J3.124~~Pin ALT-1|~~|IO_L15N_T2_DQS_13||FPGA.IO_L15N_T2_DQS_13||W8|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.126||DGND||DGND||n.a.|||||||~~Pin ALT-2|TBD

|-

|~~J3.128~~Pin ALT-3|~~|IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y7|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.130~~Pin ALT-5|~~|IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y6|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|-

|~~J3.134~~Pin ALT-1|~~|IO_L11P_T1_SRCC_13||FPGA.IO_L11P_T1_SRCC_13||U7|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.136~~Pin ALT-2|~~|IO_L11N_T1_SRCC_13||FPGA.IO_L11N_T1_SRCC_13||V7|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC~~TBD

|-

|~~J3.138||DGND||DGND||n.a.|||||||~~Pin ALT-3|TBD

|-

|~~J3.140||DGND||DGND||n.a.|||||||~~Pin ALT-5|TBD

|-

|}

----

[[Category:BORA]]

U0007

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